High-speed reduced stack dual lock circuits

Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems

Volumn 10, Issue , 2004, Pages 219-228

  Saadallah, Nisrine ^a   Kong, Xiaohua ^a   Negulescu, Radu ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA REDUCTION; ENCODING (SYMBOLS); MOS DEVICES; RELIABILITY; SYNCHRONIZATION; TRANSISTORS;

ASYNCHRONOUS CIRCUITS; COMPONENT DELAYS; DATA ENCODING;

CMOS INTEGRATED CIRCUITS;

EID: 2942640034     PISSN: 15228681     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (10)

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