Electrical waveform mediated through-mask deposition of solder bumps for wafer level packaging

Journal of the Electrochemical Society

Volumn 151, Issue 5, 2004, Pages

  Kim, Bioh ^a   Ritzdorf, Tom ^a  

^a Semitool Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEPOSITION; ELECTRIC CONDUCTANCE; ELECTRODEPOSITION; ELECTRONICS PACKAGING; ENERGY DISSIPATION; FLIP CHIP DEVICES; GRAIN SIZE AND SHAPE; MASKS; MICROPROCESSOR CHIPS; MOUNTINGS; PLATING; SEMICONDUCTOR DEVICES; WAVEFORM ANALYSIS;

ELECTRICAL WAVEFORM; MASK DEPOSITION; SOLDER BUMPS; WAFER LEVEL PACKAGING;

SOLDERING ALLOYS;

EID: 2942620210     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.1690784     Document Type: Article

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