Corner Block List Representation and Its Application to Floorplan Optimization

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 51, Issue 5, 2004, Pages 228-233

  Hong, Xianlong ^a   Dong, Sheqin ^a   Huang, Gang ^a   Cai, Yici ^a   Cheng, Chung Kuan ^b   Gu, Jun ^c  

^a TSINGHUA UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Building block layout; floorplanning representation; NP hard; placement algorithm; simulated annealing

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; MATHEMATICAL MODELS; SIMULATED ANNEALING; VLSI CIRCUITS;

BUILDING BLOCK LAYOUT; FLOORPLANNING; PLACEMENT ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 2942598371     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2004.824047     Document Type: Article

References (12)

1. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani, “VLSI module placement based on rectangle packing by the sequence pair,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 1518-1524, Dec. 1996.
2. S. Nakatake, H. Murata, K. Fujiyoshi, and Y. Kajitani, “Module pacement on BSG-structure and IC layout application,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 519-530, June 1998.
3. B.H. Gwee and M.H. Lim, “A GA with heuristic-based decoder for IC floorplanning, INTEGRATION,” VLSI J., vol. 28, pp. 157-172, 1999.
4. X. Hong, G. Huang, Y. Cai, J. Gu, S. Dong, and C.K. Cheng, “Corner block list: An effective and efficient topological representation of nonslicing floorplan,” in Proc. Int. Conf. Computer-Aided Design (ICCAD'00), 2000, pp. 8-12.
5. M. Abe, “Covering the square by squares without overlapping,” J. Japan. Math. Phys., vol. 4, no. 4, pp. 359-366, 1930.
6. T. Simizu, “Plane dividing T-configurations with consequent numbering and T-symbolism for orthogonal case,” Soc. Sci. Form A, vol. 5, no. 2, pp. 173-178, 1990.
7. K. Sakanushi, K. Midorikawa, and Y. Kajitani, “A general and fast floorplanning by reduct-seq representation,” IEICE, Tokyo, Japan, Tech. Rep. IEICE VLD2000-15, vol. 100.
8. K. Sakanushi, Y. Kajitani, and D.P. Mehta, “The quarter-state sequence floorplan representation,” IEEE Trans Circuits Syst. I, vol. 50, pp. 376-386, Mar. 2003.
9. P.N. Guo, T. Takahashi, C.K. Cheng, and T. Yoshimura, “Floorplanning using a tree representation,” IEEE Trans. Computer-Aided Design, vol. 20, pp. 281-289, Feb. 2001.
10. G. Huang, X.L. Hong, C.G. Qiao, and Y.C. Cai, “VLSI floorplan optimal design with soft blocks,” J. Computer-Aided Design Comput. Graph., vol. 11, no. 6, pp. 559-571, 1999. in Chinese.
11. Y. Ma, X. Hong, S. Dong, Y. Cai, C.K. Cheng, and J. Gu, “Floorplanning with abutment constraints and L-shaped/T-shaped blocks based on corner block list,” in Proc. 38th ACM/IEEE Design Automation Conf., June 18-22, 2001, pp. 750-775.
12. S. Zhou, S. Dong, and X. Hong et al., “ECBL: An extended corner block list with solution space including optimum placement,” in Proc. ACM Int. Symp. Physical Design, Sonoma, CA, Apr. 1-4, 2001.