Low-overhead state-retaining elements for low-leakage MTCMOS design

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 367-370

  Babighian, Pietro ^a   Benini, Luca ^b   Macii, Alberto ^a   Macii, Enrico ^a  

^a POLITECNICO DI TORINO   (Italy)

^b UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Leakage Power; MTCMOS Design; State Retention

Indexed keywords

COMPUTER SIMULATION; LEAKAGE CURRENTS; SEQUENTIAL CIRCUITS;

LEAKAGE POWER; MTCMOS DESIGN; STATE-RETENTION;

CMOS INTEGRATED CIRCUITS;

EID: 29244490655     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057749     Document Type: Conference Paper

References (5)

1. J. Kao, S. Narendra, A. Chandrakasan, "MTCMOS Hierarchical Sizing based on Mutual Exclusive Discharge Patterns," D AC-35: ACM/IEEE Design Automation Conference, pp. 495-500 San Francisco, CA, June 1998.
2. S. Mutoh, S. Shigematsu, Y. Matsuya, H. Fukuda, T. Kaneko, "A 1-V Multithreshold-Voltage CMOS Digital Signal Processor for Mobile Phone Applications", IEEE Journal of Solid-State Circuits, vol.31, no.11, pp. 1795-1802, 1996.
3. S.V. Kovosonocky, "Low-Power Circuits and Technology for Wireless Digital Systems", IBM Journal Research and & Development, vol.47, no. 2/3, pp. 1795-1802, March 2003.
4. P. Babighian, L. Benini, E. Macii, "Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating", DATE-04: IEEE 2004 Design Automation and Test in Europe, pp. 720-721, Paris, France, February 2004.
5. P. Babighian, L. Benini, A. Macii, E. Macii, "Post-Layout Leakage Power Minimization Based on Distributed Sleep Transistor Insertion", ISLPED-04: ACM/IEEE International Symposium on Low Power Electronics and Design, pp. 138-143, Newport Beach, CA, August 2004.