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Volumn 2002-January, Issue , 2002, Pages 438-442

Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

EID: 29244484901     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.2002.1158099     Document Type: Conference Paper
Times cited : (17)

References (15)
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  • 3
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  • 6
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    • On-chip inductance modeling and rlc extraction of VLSI interconnects for circuit simulation
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    • X. Qi, et al., "On-Chip Inductance Modeling and RLC Extraction of VLSI Interconnects for Circuit Simulation", Proc. of IEEE CICC, pp. 487-490, May 2000.
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    • Qi, X.1
  • 8
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  • 10
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    • Massoud, Y.1    Kawa, J.2    MacMillen, D.3    White, J.4
  • 11
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    • RLC signal integrity analysis of high-speed global interconnects
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    • X. Huang, el al., "RLC Signal Integrity Analysis of High-Speed Global Interconnects", Tech. Digest of IEDM, pp. 731-734, Dec. 2000.
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    • Huang, X.1
  • 12
    • 0035397883 scopus 로고    scopus 로고
    • Full-wave peec time-domain method for the modeling of on-chip interconnects
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    • P. J. Restle, A. E. Ruehli, S. G. Walker, and G. Papadopoulos, "Full-Wave PEEC Time-Domain Method for the Modeling of On-Chip Interconnects", IEEE Tran, on CAD, vol. 20, no. 7, pp. 877-886, July, 2001.
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  • 13
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    • An on-chip voltage regulator using switched decoupling capacitors
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    • M. Ang, R. Salem, and A. Taylor, "An On-Chip Voltage Regulator using Switched Decoupling Capacitors", Digest of ISSCC, pp. 438-439, Feb. 2000.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.