Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

IEEE Transactions on Electron Devices

Volumn 52, Issue 12, 2005, Pages 2559-2567

  Sia, Choon Beng ^a   Ong, Beng Hwee ^b   Chan, Kwok Wai ^b   Yeo, Kiat Seng ^b   Ma, Jian Guo ^b   Do, Manh Anh ^b  

^a Advanced RFIC S Pte Ltd   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Conductor eddy current; Inductance; Inductor layout optimization; Integrated RF inductor; Quality factor; Silicon RFICs; Skin effects; Spiral inductors

Indexed keywords

CMOS INTEGRATED CIRCUITS; EDDY CURRENTS; ELECTRIC INDUCTORS; INDUCTANCE; OPTIMIZATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SKIN EFFECT;

CONDUCTOR EDDY CURRENT; INDUCTOR LAYOUT OPTIMIZATION; INTEGRATED RF INDUCTOR; INTEGRATED SPIRAL INDUCTORS; PHYSICAL LAYOUT DESIGN OPTIMIZATION; QUALITY FACTOR; SILICON-BASED RFIC APPLICATIONS; SPIRAL INDUCTORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 29244479585     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.859638     Document Type: Article

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