A novel RFCMOS process monitoring test structure

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2004, Pages 45-50

  Sia, C B ^a   Ong, B H ^b   Lim, K M ^a   Yeo, K S ^b   Do, M A ^b   Ma, J G ^b   Alam, T ^c  

^a Advanced RFIC S Pte Ltd   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c Cascade Microtech Inc   (United States)

Author keywords

Process monitoring; Scribeline test structures and RFCMOS

Indexed keywords

LAYOUT STYLES; OPERATING FREQUENCIES; PROCESS MONITORING;

CAPACITORS; INTEGRATED CIRCUIT TESTING; MOSFET DEVICES; OPTICAL INTERCONNECTS; PROCESS CONTROL; SEMICONDUCTOR DIODES; VARACTORS;

CMOS INTEGRATED CIRCUITS;

EID: 3042654672     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. L. E. Larson, "Integrated Circuit Technology Options for RFIC's - Present Status and Future Directions", IEEE Journal of Solid-State Circuits, vol. 32, no. 3, pp. 387-397, Mar 1998.
2. B. Razavi, "CMOS Technology Characterization for Analog and RF Design", IEEE Journal of Solid-State Circuits, vol. 34, no. 3, pp. 268-276, Mar 1999.
3. Ewout P. Vandamme, Dominique M. M.-P. Schreurs and Cees van Dinther, "Improved Three-Step De-Embedding Method to Accurately account for the influence of Pad Parasitics in Silicon On-Wafer RF Test Structures," IEEE Transactions on Electron Devices, vol. 48, no. 4 pp. 737-742, Apr 2001.