Width minimization of two-dimensional CMOS cells using integer programming

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 660-667

  Gupta, Avaneendra ^a   Hayes, John P ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; OPTIMIZATION; TRANSISTORS;

CELL WIDTH; DIFFUSION ROWS; TWO DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CELLS; WIDTH MINIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0030410343     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)