Future challenges in electronics packaging: Meeting the requirements of high density and high frequency facing the industry down the road

IEEE Circuits and Devices Magazine

Volumn 14, Issue 2, 1998, Pages 45-54

  Chang, Chi Shih ^a   Oscilowski, Alex ^a   Bracken, Ronald C ^b  

^a SEMATECH   (United States)

^b Semiconuctor Research Corporation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED SOFTWARE ENGINEERING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT LAYOUT; MULTICHIP MODULES; PRINTED CIRCUIT BOARDS; SUBSTRATES;

THERMAL MANAGEMENT;

ELECTRONICS PACKAGING;

EID: 0032021461     PISSN: 87553996     EISSN: None     Source Type: Journal    
DOI: 10.1109/101.666591     Document Type: Article

References (33)

1. The National Technology Roadmap for Semiconductors, 1997 Edition, Semiconductor Industry Association, San Jose, CA. November 1997. See http://notes.sematech.org/97pelec.htm
2. The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, December 1994.
3. C.S. Chang, R. Bracken, and A. Oscilowski, "The 1997 National Technology Roadmap for Semiconductors - Future Challenges in Electronic Assembly and Packaging." to be published in Solid-State Technology.
4. National Electronics Manufacturing Technology Roadmaps, National Electronics Manufacturing Initiative, Inc., Herndon, VA, December 1996.
5. The National Technology Roadmap for Electronic Interconnections, The Institute for Interconnecting and Packaging Electronic Circuits (IPC), Northbrook, IL, September 1997.
6. G. Harman, Wire Bonding in Microelectronics Materials, Processes, Reliability, and Yield, Second Edition, McGraw-Hill, New York, NY, 1997.
7. C.S. Chang, "Heuristic Equations for Semiconductor and Packaging Technology Evolution Projection," IBM Unclassified Technical Report, TR 01.C772, November 21, 1994.
8. C.S. Chang and A. Oscilowski, "U.S. Packaging Trends," SEMICON/Japan'96, Proceedings, International Packaging Strategy Symposium, pp. 1-1 to 1-17, December 3, 1996, Tokyo, Japan
9. P.A. Totta, S. Khadpe, N.G. Koopman, T.C. Reiley and M.J. Sheaffer, "Chip-to-Package Interconnections," in Microelectronics Packaging Handbook, Part II - Semiconductor Packaging, ed. R. R. Tummala, E.J. Rymaszewski and A.G. Klopfenstein, pp. 11-129 to 11-283. Chapman & Hall, NY 1997
10. H. Yamamoto, A. Fujisaki and S. Kikuchi, "MCM and Bare Chip Technology for a Wide Range of Computers, "Proc. 46th Components and Technology Conferences, pp. 133-138, May 28-31, 1996, Orlando, FL
11. D.S. Patterson, P. Elenius and J.A. Leal, "Wafer Bumping Technologies - a Comparative Analysis of Solder Deposition Processes and Assembly Considerations, " Proc. International Intersociety Electronic & Photonic Packaging Conference (INTERpack'97), pp.337-351, June 15-19, 1997, Kohala Coast, HI
12. B.D. Knowlton, J.J. Clement, R.I. Frank, and C.V. Thompson, "Coupled Stress Evolution in Polygranular Clusters and Bamboo Segments in Near-Bamboo Interconnects," Materials Research Society Symposium Proc. Vol. 391, pp. 189-196, April 17-21, 1995, San Francisco, CA.
13. P.-H. Wang, C. Lee, D. Jawarani, H. Kawasaki and P. S. Ho, "A Comparative Study on Electromigration Failure Mechanism between Near-Bamboo and Bamboo Al(Cu) Two-level Structure, "Materials Research Society Symposium Proc. Vol. 391, pp. 265-270, April 17-21, 1995, San Francisco, CA.
14. In Japan, the 40 mm QFP has been used for 504 leads at 0.3 mm OLB. Please see Roadmap on Semiconductor Packaging Technologies, (in Japanese) Electronic Industries Association of Japan, Electronic Devices Mounting Technical Committee, December 1996.
15. K. Puttlitz and W.F. Shutler, "C-4/BGA Comparison with Other MLC Single Chip Package Alternatives, " Proc. 44th Electronic Components and Technology Conferences, pp. 16-21, May 1 - 4, 1994, Washington, DC.
16. Y. Tsukada, S. Tsuchida and Y. Mashimoto, "Surface Laminar Circuit Packaging," Proc. 42nd Electronic Components and Technology Conferences, pp. 22-27, May 18-20, 1992, San Diego, CA.
17. O. Powell and A. K. Trivedi, "Flip-Chip on FR-4 Integrated Circuit Packaging," Proc. 43th Electronic Components and Technology Conferences, pp. 182-186, June 1-4, 1993. Orlando, FL.
18. Y. Tsukada, "The Strategy and Status of a Bare Chip Packaging," Proc. 1997 IEMT/IMC Symposium, pp. 5-9, April 16-18, 1997, Omiya, Japan.
19. E. Jan Vardaman and T. Goodman, "Flip Chip Market Trends and Infrastructure Limitations." Proc. 1997 IEMT/IMC Symposium, pp. 37-40, April 16-18, 1997, Omiya, Japan.
20. L.-S. Su, M. Louis and C. Reher, "Cost Analysis of Chip Scale Packaging," Proc. 1997 IEMT Symposium, pp. 216-223, October 13-15, 1997, Austin TX.
21. E. Chieh, J. Lykins, C. Ho, L. Moresco, M. Koblis, et al., "Development of Large Area Processing for Thin Film Substrates," Proc. 6th International Conference on Multichip Modules, pp. 234-239, April 2-4, 1997, Denver CO.
22. High Density Printed Wiring Board - Microvia Evaluation, October Project Phase I, Round 2 Report. 97071501-G, Interconnection Technology Research Institute, The Institute for Interconnecting and Packaging Electronic Circuits (IPC), Northbrook, IL, July 15, 1997.
23. J Rasul, W. Bratschun and J. McCowen, "Microvia Bare Board Reliability Assessment," Proc. Technical Conference, IPC Expo'97, pp. S17-5-1 to S17-5-6, March 9-13, 1997, San Jose, CA.
24. J. Paulus and M. Petti, "Microvia Materials: Enablers for High Density Interconnects," Proc. Technical Conference, IPC Expo'97, pp. S17-2-1 to S17-2-7, March 9-13, 1997, San Jose, CA.
25. T.Y. Wu, Y. Tsukada and W.T. Chen, "Materials and Mechanics Issues in Flip-Chip Organic Packaging," Proc. 46th Electronic Components and Technology Conferences, pp. 524-534, May 28-31, 1996, Orlando, FL.
26. S. Mizumoto, Y. Tsukada, and I. Shishido, "Analysis of Stress Condition for Organic Multi-Chip Package," Proc. International Intersociety Electronic & Photonic Packaging Conference (INTERpack'97), pp. 113-117, June 15-19, 1997, Kohala Coast, HI.
27. R.E. Simons, V.W. Antonetti, W. Nakayama, and S. Oktay, "Heat Transfer in Electronic Packages," in Microelectronics Packaging Handbook, Part I - Technology Drivers, ed. R.R. Tummala, E.J. Rymaszewski, and A.G. Klopfenstein, pp. I-314 to I-403, Chapman & Hall, New York, NY, 1997.
28. E.E. Davidson, G.A. Katopis and T. Sudo, "Package Electrical Design," in Microelectronics Packaging Handbook, Part I - Technology Drivers, ed. R.R. Tummala, E.J. Rymaszewski and A.C. Klopfenstein, pp. I-199 to I-313, Chapman & Hall, New York, NY, 1997
29. C.S. Chang, "Electrical Design Methodologies," in Electronic Materials Handbook, Volume 1: Packaging, edited by M.L. Minges, pp. 25-44, ASM International, Metals Park, Ohio, 1989.
30. The backward coupling coefficient in ref. 29 shows a strong dependence on the ratio of the thickness of the dielectric to the spacing between signal lines, and an intermediate dependence on the ratio of the width of a signal line to the spacing between signal lines. For the ceramic substrate, when the spacing between signal line is equal to the thickness of the dielectric, which is 2.8X of the width of a signal line, the ratio of the width of a signal line to the spacing between signal lines is reduced from 1.0 to 0.36. The backward coupling coefficient is reduced from 136 mV/volt to 119 mV/volt. If 136 mV/volt is acceptable, the spacing between signal lines can be reduced from 2.8X to 2.3X the line width. The impact on wiring density is lessened somewhat.
31. C.S. Chang, A.P. Agrawal and N. Feilchenfeld, "Thin Dielectric Laminate Design and Assessment," Proc. of the Technical Program, NEPCON West'94, pp. 89-110, February 27 to March 4, 1994, Anaheim, CA.
32. S.B. Huq, "An Overview of LVDS Technology," National Semiconductor Application Note 971, November 1994. See http://www.nsc.com/apnotes/
33. Y.A Cengel, Heat Transfer, Chapter 14, "Cooling of Electronic Equipment," pp. 863-944, McCraw-Hill, New York, 1998.