Design of high-performance power-aware asynchronous pipelined circuits in MOS Current-Mode Logic

Proceedings - International Symposium on Asynchronous Circuits and Systems

Volumn , Issue , 2005, Pages 23-32

  Kwan, Tin Wai ^a   Shams, Maitham ^a  

^a CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER UTILIZATION; MOS DEVICES;

ASYNCHRONOUS PIPELINES CIRCUITS; POWER DISSIPATION;

LOGIC CIRCUITS;

EID: 28444471615     PISSN: 26431394     EISSN: 26431483     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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9. T.W. Kwan, Design and Implementation of Multi-GHz Energy-Efficient Asynchronous Pipelined Circuits in MOS Current-Mode Logic. M.A.Sc. thesis, Carleton University, 2004.