Power-delay trade-offs in SCL gates

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Alioto, M ^a   Palumbo, G ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC RESISTANCE; LOGIC DESIGN; MATHEMATICAL MODELS; MOSFET DEVICES; OPTIMIZATION; POWER CONVERTERS; SPURIOUS SIGNAL NOISE;

MIXED SIGNAL INTEGRATED CIRCUITS; NOISE MARGIN MODEL; POWER DELAY; POWER DISSIPATION; SOURCE COUPLED LOGIC GATES;

LOGIC GATES;

EID: 0036287636     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Digital circuit techniques for mixed analog/digital circuits applications
2. Synthesis techniques for CMOS folded source-coupled logic circuits
3. Design guidelines for CMOS current steering logic
4. Current mode BiCMOS folded source-coupled logic circuits
5. CMOS current steering logic for low-voltage mixed-signal integrated circuits
6. Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal Ics
7. Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits
8. Performance of CMOS differential circuits
9. Predicting propagation delay in SCL gates