150μm pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004

Volumn , Issue , 2004, Pages 126-131

  Yoon, Seung Wook ^a   Kripesh, Vaidyanathan ^a   Yu, Li Hong ^a   Iyer, Mahadevan K ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; COPPER PLATING; DEPOSITION; ELECTRONICS PACKAGING; ENCAPSULATION; FAILURE ANALYSIS; INTERCONNECTION NETWORKS; MICROSTRUCTURE; POLYMERS; SOLDERED JOINTS; SOLDERING; STRESSES;

DAMASCENE PROCESS; SHEAR TESTS; SOLDER INTERCONNECTION; WAFER INTEGRATION TECHNOLOGY;

FLIP CHIP DEVICES;

EID: 28444464846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Lei L. Mercado, Cindy Goldberg, Shun-Meen Kuo, Tien-Yu Lee and Scott K. Pozder, "Analysis of flipchip packaging challenges on copper/low-k interconnectes," IEEE transactions on device and materials reliability, vol 3, no.4, Dec. 2003
2. International Technology Roadmap for Semiconductors, 2001 and 2003 Update.
3. Senug Wook Yoon, Vaidyanathan Kripesh, Wong Wai Kwan, Li Chao Yong, Chen Xian Tong, Gui Dong, Ingnatius J Rasiah and Mahadevan K. Iyer,"UBM Integrity Studies on Copper/low-k Dielectrics for Fine Pitch Flip Chip Packaging", Proceeding of 53rd Electronic Components & Technology Conference, New Orleans, US (2003).
4. Surface Evolver, http://www.geom.uiuc.edu/software/download/evolver. html, http://www.susqu.edU/facstaff/b/brakke/evolver/
5. Seung Wook Yoon, Vaidyanathan Kripesh, Li Hongyu,Li Chao Yong, Su Yong Ji Jeffrey and Mahadevan K. Iyer, "Flipchip Bump Integrity with Copper/Ultra Low-k Dielectrics for fine pitch Flipchip Packaging", Proceeding of the 54th Electronic Components Technology Conference(ECTC), Las Vegas, US (2004).