A spread spectrum clock generator for emi reduction

IEICE Transactions on Electronics

Volumn E84-C, Issue 12, 2001, Pages 1959-1966

  Chen, Hung Wei ^a   Wu, Jiin Chuan ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

EMI; Frequency synthesizer; Spread spectrum; SSDPLL; Variation average

Indexed keywords

EID: 0344078194     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (5)

1. K.B. Harclin, J.T. Fessler, N.L. Webb, J.B. Berry, A.L. Cable, and M.J. Pulley, "Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility," Electromagnetic Compatibility, IEEE 1997 International Symposium, pp.302-307, 1997.
2. H.-S. Li, Y.-C. Cheng, and D. Puar, "Dual-loop spread-spectrum clock generator," Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, 1999 IEEE International, pp.184-185, 1999.
3. R.E. Best, Phase-Locked Loops, Theory, Design and Application, 3rd ed., McGraw-Hill, New York, NY, 1997.
4. B. Razavi, Monolithic Phase-Locked Loop and Recovery Circuits Theory and Design, IEEE Press, 1996.
5. I.A. Young, J.K. Greason, and K.L. Wong, "A PLL clock generator with 5 to 110 MHz of lock range for microprocessors," IEEE J. Solid-State Circuits, vol.27, no.11, pp.1599-1607, Nov. 1992.