A 27-mW 3.6-Gb/s I/O Transceiver

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 99-102

  Wong, Koon Lun Jackie ^a   Mansuri, Mozhgan ^a   Hatamkhani, Hamid ^a   Yang, Chih Kong Ken ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Comparator; Data recovery; I O; Low power; Receiver; Transceiver

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA ACQUISITION;

DATA RECOVERY;

TRANSCEIVERS;

EID: 0141426758     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. F. Yang, J.H. O'Neill, D. Inglis, and J. Othmer, "A CMOS Low-Power Multiple 2.5-3.125-Gb/s Serial Link Macrocell for High IO Bandwidth Network ICs," IEEE JSSC, vol. 37, pp. 1813-1821, Dec 2002
2. M.-J. Lee, W.J. Daily, and P. Chiang, "Low-Power Area-Efficient High-Speed 170 Circuit Techniques," IEEE JSSC, vol. 35, pp. 1591-1599, Nov 2000.
3. M. Fukaishi, et al., "A 20-Gh/s CMOS Multichannel Transmitter and Receiver Chip Set for Ultra-High-Resolution Digital Displays," IEEE JSSC, vol. 35, pp. 1611-1618, Nov 2000.
4. Hamid Hatamkhani, Koon-Lun Jackie Wong, Robert Drost, and Chih-Kong Ken Yang, "A 4mW/Gbps I/O Transmitter," is submitted to 2003 Symposium on VLSI Circuits.
5. M.J.M. Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, "Matching properties of MOS transistors," IEEE JSSC, vol. 24, pp. 1433-1440, 1989.
6. W. Ellersick, C-K.K. Yang, M. Horowitz, W.J. Dally, "GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link," 1999 Symposium on VLSI Circuits Digest of Papers, pp. 49-52, June 1999.
7. M. Mansuri, et al., "A Low-Power Low-Jitter Adaptive-Bandwidth PLL and Clock buffer," will be presented in ISSCC 2003