Secure scan: A design-for-test architecture for crypto chips

Proceedings - Design Automation Conference

Volumn , Issue , 2005, Pages 135-140

  Yang, Bo ^a   Wu, Kaijie ^b   Karri, Ramesh ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

^b UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

Author keywords

Crypto Hardware; Scan based DFT; Security; Testability

Indexed keywords

CRYPTO CHIPS; CRYPTO HARDWARE; SCAN-BASED DFT; TESTABILITY;

ALGORITHMS; COMPUTER HARDWARE; CRYPTOGRAPHY; DATA PRIVACY; DESIGN FOR TESTABILITY; SECURITY OF DATA; STANDARDS;

MICROPROCESSOR CHIPS;

EID: 27944506419     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. S. Mangard, M. Aigner and S. Dominikus, A Highly Regular and Scalable AES Hardware Architecture, IEEE Transactions on Computer, vol. 52, no.1, pp. 483-491, April 2004.
2. M.L. Bushnell and V.D. Agrawal, Essentials of Electronic Testing, Kluwer Academic Publishers, 2000.
3. D, Josephson and S. Poehhnan, Debug methodology for the McKinley processor, International Test Conference, pp.451-460, 2001
4. B. Yang, K. Wu and R. Karri, Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard, International Test Conference, pp.339-344, 2004
5. R. Goering, Scan Design Called Portal for Hackers, EE Times, Oct. 2004. http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=51200146
6. Maestra Comprehensive Guide to Satellite TV Testing, 2002. http://www.maestra.tv/downloads/Maestra_Guide.pdf
7. O. Kömmerling, M. G. Kühn, Design Principles for Tamper-Resistant Smartcard Processors, USENK Workshop on Smartcard Technology, pp.9-20, May.
8. R. J. Easter, E. W. Chencinski, E. J. D'Avignon, S. R. Greenspan, W. A. Merz and C. D. Norberg, S/390 Parallel Enterprise Server CMOS Cryptographic Coprocessor, IBM Journal of Research and Development, Vol 43, pp.761-776, 1999
9. D. Hély, F. Bancel, ML Flottes, B. Rouzeyre, M. Renovell and N. Berard, Scan Design and Secure Chip, IEEE International On-Line Testing Symposium pp.219-226, 2004.
10. R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber and W. Fichtner, A 177Mb/sec VLSI implementation of the international data encryption algorithm, IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 303-307, March, 1994.
11. National Bureau of Standards, Security Requirements for Cryptographic Modules, Federal Information Processing Standards Publication FIPS PUB 140-2, 2002.
12. Biham and A. Shamir, Differential Fault Analysis of Secret Key Cryptosystems, CRYPTO, pp. 156-171, 1991.