A signal integrity test bed for PCB buses

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2004, Pages 132-137

  Ren, Jihong ^a   Greenstreet, Mark R ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

EQUALIZATION FILTERS; GRAPHIC CARDS; SIGNAL INTEGRITY; TEST BEDS;

COMPUTER GRAPHICS; COMPUTER SIMULATION; ELECTRIC FILTERS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; PRINTED CIRCUIT BOARDS; SIGNAL PROCESSING;

INTEGRATED CIRCUIT TESTING;

EID: 17644381997     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

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