A theoretical yield model for assembly process of area array solder interconnect packages with experimental verification

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 28, Issue 4, 2005, Pages 344-354

  Kim, Chunho ^a   Baldwin, Daniel F ^b  

^a INTEL CORPORATION   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Area array; Assembly; Contact; Eutectic balls; Experiment; Interconnect; Modeling; Package; Solder joints; Statistical variations; Wetting; Yield

Indexed keywords

ASSEMBLY; FLIP CHIP DEVICES; MATHEMATICAL MODELS; SOLDERED JOINTS; STATISTICAL METHODS; SUBSTRATES; WETTING;

AREA ARRAY SOLDER INTERCONNECT PACKAGES; EUTECTIC BALLS; STATISTICAL VARIATIONS; THEORETICAL YIELD MODEL;

CHIP SCALE PACKAGES;

EID: 27844509133     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2005.856659     Document Type: Article

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