Models to estimate printed circuit board fabrication yield during the design stage

Journal of Electronics Manufacturing

Volumn 9, Issue 3, 1999, Pages 191-202

  Giachetti, Ronald E ^a  

^a FLORIDA INTERNATIONAL UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ESTIMATION; POISSON DISTRIBUTION; PRINTED CIRCUIT DESIGN; PRINTED CIRCUIT TESTING; QUALITY CONTROL;

BOARD LAYOUT; BOARD ROUTING; DESIGN FOR MANUFACTURING; PROCESS CAPABILITY; PROCESS YIELD;

PRINTED CIRCUIT MANUFACTURE;

EID: 0033293978     PISSN: 09603131     EISSN: None     Source Type: Journal    
DOI: 10.1142/S0960313199000118     Document Type: Article

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