A core generator for arithmetic cores and testing structures with a network interface

Journal of Systems Architecture

Volumn 52, Issue 1, 2006, Pages 1-12

  Bakalis, D ^a,c,d   Adaos, K D ^a,d,e   Lymperopoulos, D ^a   Bellos, M ^a   Vergos, H T ^a   Alexiou, G Ph ^a,b,d,f,g   Nikolos, D ^a,b  

^a UNIVERSITY OF PATRAS   (Greece)

^b University of Patras and Computer Technology Institute   (Greece)

^c Physics Department   (Greece)

^d IEEE   (Greece)

^e ATMEL CORPORATION   (United States)

^f Atmel Corporation ^*

^g Microelectronics(VLSI) Lab

Author keywords

[No Author keywords available]

Indexed keywords

NETWORK INTERFACE; PATTERN GENERATORS; POWER CHARACTERS; SQUARE ROOTING;

COMPUTER ARCHITECTURE; INTERFACES (MATERIALS); MACHINE DESIGN; MATHEMATICAL OPERATORS; SYNTHESIS (CHEMICAL);

DIGITAL ARITHMETIC;

EID: 27844462559     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2004.12.006     Document Type: Article

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