EmGen - A module generator for logic emulation applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 7, Issue 4, 1999, Pages 488-492

  Fang, Wen Jong ^a   Wu, Allen C H ^b   Chen, Duan Ping ^c  

^a Y Explorations Inc   (United States)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^c Arcadia Design Systems Inc   (United States)

Author keywords

Complex macros; FPGA synthesis; Logic emulation; Module generation

Indexed keywords

LOGIC PROGRAMMING; MACROS; MICROPROCESSOR CHIPS;

LOGIC EMULATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0033280921     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.805756     Document Type: Article

References (13)

1. M. Butts, J. Batcheller, and J. Varghese, "An efficient logic emulation system," in Proc. Int. Conf. Comput. Design, 1992, pp. 138-141.
2. S. Walters, "Computer-aided prototyping for ASIC-based systems," IEEE Design and Test Comput., pp. 4-10, June 1991.
3. J. Gateley, "Logic emulation aids design process," ASIC & EDA, July, 1994.
4. J. Kumar, N. Strader, J. Freeman, and M. Miller, "Emulation verification of the Motorola 68060," in Proc. Int. Conf. Comput. Design, 1995, pp. 150-158.
5. J. Gateley et al., "UltraSPARC-1 emulation," in Proc. 32nd Design Automation Conf., 1995, pp. 13-18.
6. G. Ganapathy, R. Narayan, G. Jorden, D. Fernandez, M. Wang, and J. Nishimura, "Hardware emulation for functional verification of K5," in Proc. 33rd Design Automation Conf., 1996, pp. 315-318.
7. M. Butts, "Future directions of dynamically reprogrammable systems," in Proc. Customer Integrated Circuits Conf., 1995.
8. XACT Libraries Guide. San Jose, CA: Xilinx, 1994.
9. D. Gajski, N. Dutt, A. Wu, and S. Lin, High-level Synthesis. Norwell, MA: Kluwer, 1992.
10. C. M. Fiduccia and R. M. Mattheyses, "A linear time heuristic for improving network partitions," in Proc. 19th Design Automation Conf., 1982, pp. 175-181.
11. W.-J. Fang and A. C.-H. Wu, "A hierarchical functional structuring and partitioning algorithm for multiple-FPGA implementations," in Int. Conf. Computer-Aided Design, 1996, pp. 638-643.
12. HDL-ICE User's Guide Ver. 1.0. Mountain View, CA: Quickturn Design Syst., 1995.
13. Quest User's Guide Ver. 4.0. Mountain View, CA: Quickturn Design Syst., 1995.