On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 1, 1998, Pages 114-121

  Aberbour, Mourad ^a   Houelle, Alain ^a   Mehrez, Habib ^a   Vaucher, Nicolas ^a   Guyot, Alain ^b  

^a UNIVERSITÉ PIERRE ET MARIE CURIE   (France)

^b TIMA LABORATORY   (France)

Author keywords

Arithmetic unit; Computer aided design; Division; IEEE 754 standard; Square root

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; DIGITAL ARITHMETIC; DIVIDING CIRCUITS (ARITHMETIC); INTEGRATED CIRCUIT LAYOUT; STANDARDS;

SIGNED BINARY DIGIT REPRESENTATION; SOFTWARE PACKAGE GENOPTIM;

DIGITAL INTEGRATED CIRCUITS;

EID: 0032028338     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.661253     Document Type: Article

References (19)

1. A. Houelle, H. Mehrez, and N. Vaucher, "On portable macro-cell generators using the fully 754-IEEE standard," in Proc. ICSPAT'94, Dallas, TX, Oct. 18-21, 1994, V2, pp. 1749-1754.
2. _, "Méhodologie de conception de générateurs portables de macroblocs fonctionnels optimisés en surface et en performance," MASI report, Dec. 1993.
3. ANSI/IEEE, "IEEE standard for binary floating-point arithmetic," ANSI/IEEE Trans., Std. 354-1985.
4. J. J. F. Cavanagh, "Digital computer arithmetic, design and implementation," in Computer Science Series. New York: McGraw-Hill, 1984.
5. A. Avizienis, "Signed number representation for fast parallel arithmetic," IRE Trans. Electron. Comput., vol. EC-10, Sept. 1961.
6. J. E. Robertson, "The correspondence between methods of digital division and multiplier recoding procedures," IEEE Trans. Comput., vol. C-19, Aug. 1970.
7. K. D. Tocher, "Techniques of multiplication and division for automatic binary computers," Quart. J. Mech. Appl. Math., vol. 11, no. 3, 1958.
8. A. Vandemeulebroecke et al., "A new carry free division algorithm and application to a single chip RSA processor," in Proc. ESSCIRC'89, Vienna, Austria, 1989.
9. J. William and V. C. Hamacher, "A linear-time divider array," Canadian Elec. Eng. J., vol. 6, no. 4, 1981.
10. I. Moussa, A. Guyot, and P. Rost, "Design and comparison of GaAs and Cmos redundant dividers," in Proc. ESSCIRC'93, Sevilla, Spain, 1993.
11. R. Brent and H. T. Kung, "Regular layout for parallel adders," IEEE Trans. Comput., vol. C-31, 1982.
12. D. Goldberg, "What every computer scientist should know about floating-point arithmetic," ACM Comput. Surv., vol. 23, no. 1, Mar. 1991.
13. D. Johansen, "Bristle blocks: A silicon compiler," in Proc. 16th ACM IEEE DAC, San Diego, CA, June 1979.
14. A. Greiner and F. Pêcheux, "ALLIANCE: A complete set of CAD tools for teaching VLSI design," in Proc. Third Eurochip Workshop, 1992, pp. 230-237.
15. The VHDL Language Reference Manual, Intermetrics, Inc., version 7.2, Aug. 1985.
16. A. Compan, V. Delorme, J.-A. François, H. Mehrez, and F. Pêcheux, "F-Risc: A 32 bits floating-point unit integrated in a Risc processor for embedded system," in Proc. ICM92, Monastir, Dec. 19-21, 1992, pp. 6.1.2.1-6.1.2.4.
17. S. E. McQuillan and J. V. McCanny, "New algorithms and VLSI architectures for SRT division and square root," in Proc. IEEE Symp. Comput. Arithmetic, 1993, pp. 80-86.
18. J.-M. Muller, "Arithmétique des ordinateurs, opérations et fonctions élémentaires," Masson, 1989.
19. A. Guyot, L. Montalvo, A. Houelle, H. Mehrez, and N. Vaucher, "Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers," in Proc. 8th IEEE Int. Conf. VLSI Design, New Delhi, India, Jan. 1995.