IC modeling for yield-aware design with variable defect rates

Proceedings - Annual Reliability and Maintainability Symposium

Volumn , Issue , 2005, Pages 489-495

  Kumar, Vinu Vijay ^a,b,c,d   Lach, John ^a,b,c,d,e  

^a UNIVERSITY OF VIRGINIA   (United States)

^b University of Virginia   (United States)

^c IEEE   (United States)

^d IEEE Computer Society ^*  (United States)

^e ACM   (United States)

Author keywords

Semiconductor burn in test; Yield modeling; Yield aware design

Indexed keywords

INTEGRATED CIRCUIT (IC) DEVICES; SEMICONDUCTOR BURN-IN TESTS; YIELD MODELING; YIELD-AWARE DESIGN; SEMICONDUCTOR BURN-IN TEST;

INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; MATHEMATICAL MODELS; PROBLEM SOLVING; PROCESS CONTROL; QUALITY CONTROL; SEMICONDUCTOR MATERIALS; THROUGHPUT;

INTEGRATED CIRCUITS;

EID: 27744593005     PISSN: 0149144X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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