Ultimate CMOS ULSI Performance

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1993, Pages 115-118

  Nowak, Edward J ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MOSFET DEVICES; POWER SUPPLY CIRCUITS;

% REDUCTIONS; ACTIVE POWER; CMOS TECHNOLOGY; MOSFETS; NEW APPROACHES; PASSIVE POWER; PERFORMANCE; POWER CONSTRAINTS; POWER SUPPLY VOLTAGE; SCALING THEORIES;

THRESHOLD VOLTAGE; ULSI CIRCUITS;

ACTIVE POWER; SCALE REDUCTION; SCALING THEORY;

EID: 0027850958     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. R.H.Dennard, F.H.Gaensslen, H.Yu, V.L.Rideout, E.Bassous, A.R.LeBlanc, "Design of ion-implanted MOSFET's with very small dimensions," IEEE J. Solid State Circuits, SC-9, 256 (1974)
2. A.Perrara, J.Krusius, "Ultimate CMOS density limits: measured source drain resistance in ultra small devices," IEDM Tech. Dig. 1989, p. 625.
3. D.Liu, C.Svensson, "Trading speed for low power by choice of supply and threshold voltages," IEEE J. Solid-State Circuits, V.28, No. 1 (1993).
4. K.Shimohigashi, K.Seki, "Low-voltage ULSI design," IEEE J. Solid-Stale Circuits, V.28, No. 4 (1993).
5. D.A.Antoniadis and J.E.Chung, "Physics and technology of ultra short channel MOSFET devices," IEDM Tech. Dig. 1991, p. 21.