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Volumn , Issue , 2005, Pages 573-576

A multi-phase 10 GHz VCO in CMOS/SOI for 40 Gbits/s SONET OC-768 clock and data recovery circuits

Author keywords

High speed integrated circuits; Jitter; Phase noise; Silicon on insulator technology; SONET; Voltage controlled oscillators

Indexed keywords

FREQUENCY TUNING; HIGH-SPEED INTEGRATED CIRCUITS; RING AMPLIFIERS; SONET;

EID: 27644507278     PISSN: 15292517     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RFIC.2005.1489878     Document Type: Conference Paper
Times cited : (10)

References (9)
  • 3
    • 27644465075 scopus 로고    scopus 로고
    • The control of jitter and wander in the optical transport network
    • October
    • "The control of jitter and wander in the optical transport network," ITU-T Recommendation G.8251, Draft revision 04.0, October 2001.
    • (2001) ITU-T Recommendation G.8251, Draft Revision 04.0
  • 6
    • 0346342381 scopus 로고    scopus 로고
    • A 40-Gb/s clock and data recovery circuit in 0.18-nm CMOS technology
    • December
    • J. Lee and B. Razavi, "A 40-Gb/s clock and data recovery circuit in 0.18-nm CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 2181-2190, December 2003.
    • (2003) IEEE J. Solid-state Circuits , vol.38 , Issue.4 , pp. 2181-2190
    • Lee, J.1    Razavi, B.2
  • 8
    • 0036504292 scopus 로고    scopus 로고
    • Tail current noise suppression in RF CMOS VCOs
    • March
    • P. Andreani and H. Sjöland, "Tail current noise suppression in RF CMOS VCOs," IEEE J. Solid-State Circuits, vol. 37, no. 3, pp. 342-348, March 2002.
    • (2002) IEEE J. Solid-state Circuits , vol.37 , Issue.3 , pp. 342-348
    • Andreani, P.1    Sjöland, H.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.