Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn , Issue , 2005, Pages 64-71

  Brodsky, Mary Jane ^a   Halle, Scott ^a   Jophlin Gut, Vickie ^a   Liebmann, Lars ^a   Samuels, Don ^a   Crispo, Gary ^b   Nafisi, Kourosh ^b   Ramani, Vijay ^b   Peterson, Ingrid ^b  

^a IBM MICROELECTRONICS   (United States)

^b KLA TENCOR CORPORATION   (United States)

Author keywords

Brightfield imaging wafer inspection techniques; Design for Manufacturing; Process window verification and qualification

Indexed keywords

ERROR ANALYSIS; MICROPROCESSOR CHIPS; PHOTOLITHOGRAPHY; PRODUCT DEVELOPMENT; RANDOM PROCESSES;

BRIGHTFIELD IMAGING WAFER INSPECTION TECHNIQUE; DESIGN FOR MANUFACTURING; PROCESS WINDOW VERIFICATION AND QUALIFICATION; RESOLUTION ENHANCEMENT TECHNIQUES (RET);

SILICON;

EID: 27644494160     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Chris M. Jones, et. al., "Faster qualification of 193-nm resists for 100-nm development using photo cellmonitoring", SPIE Microlithography, 2003.
2. L. Liebmann et al., "High-performance circuit design for the RET-enabled 65 nm technology node," Design and Process Integration for Microcelectronic Manufacturing III, SPIE 5379, 2004
3. L. Liebmann, S. Mansfield, J. Bruce, M. Cross, I. Graur, A. McGuire, J. Krueger, D. Sunderling, "Optimizing style options for sub-resolution assist features," in Proc. SPIE (C. Progler, ed.), vol 4346, SPIE, 2001.