Faster qualification of 193-nm resists for 100-nm development using photo cell monitoring

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5038 II, Issue , 2003, Pages 1231-1241

  Jones, Chris M ^a   Kallingal, Chidam ^a   Zawadzki, Mary ^a   Jeewakhan, Nazneen ^a   Kaviani, Nazila ^a   Krishnan, Prakash ^a   Klaum, Art ^b   Van Ess, Joel ^b  

^a CYPRESS SEMICONDUCTOR   (United States)

^b KLA TENCOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEFECTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; PHOTOLITHOGRAPHY; PHOTORESISTS; SILICON WAFERS; TEMPERATURE; WSI CIRCUITS;

DEFECT DENSITY; PHOTO CELL MONITORING; POST EXPOSURE BAKE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0141500090     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.504591     Document Type: Conference Paper

References (4)

1. Ingrid B. Peterson, Defect Reduction Methodology in the Lithography Module, XIII Annual Meeting of SPIE Microlithography Conference, p. 520 (1999)
2. Kay Lederer, et al., Automated Micro Defect Monitoring for 300mm Lithography, Olin Interface 2002, p.XXX (2002)
3. Eric H. Bokelberg, et al., Photocluster Defect Learning and Develop Process Optimization, Olin Interface 96, p.127 (1996)
4. Ingrid Peterson, et al., Lithography Defects: Reducing and Managing Yield Killers Through Photo Cell Monitoring, Yield Management Solutions 2-3 (Summer 2000)