Compact modeling of FinFETs featuring independent-gate operation mode

2005 IEEE VLSI-TSA - International Symposium on VLSI Technology - VLSI-TSA-TECH, Proceedings of Technical Papers

Volumn , Issue , 2005, Pages 120-121

  Lin, C H ^a   Xi, X ^a   He, J ^a   Chang, L ^b   Williams, R Q ^c   Kelchen, M B ^b   Haensch, W E ^b   Dunga, M ^a   Balasubramanian, S ^a   Niknejad, A M ^a   Chan, M ^d   Hu, C ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM MICROELECTRONICS   (United States)

^d HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27144506585     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2005.1497105     Document Type: Conference Paper

References (8)

1. D. Frank et al., IEDM Tech. Dig., p.553, 1992.
2. X. Huang et al., IEDM Tech. Dig., p.67, 1999.
3. J. Kedzierski et al., IEDM Tech. Dig., p.247, 2002.
4. I. Y. Yang et al, IEEE TED, vol. 44 (5), p. 822, 1997.
5. Y. Liu et al., IEEE EDL, vol. 25 (7), p.510, 2004.
6. Y. Taur, IEEE TED, vol. 48(12), p.2861, 2001.
7. S. R. Banna et al., IEEE TED, vol. 42(11), 1995.
8. M. Chan et al., MSM, p. 270, 2003.