메뉴 건너뛰기




Volumn 3603, Issue , 2005, Pages 326-341

Formal verification of a SHA-1 circuit core using ACL2

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; SMART CARDS; SPECIFICATIONS; STANDARDS; THEOREM PROVING;

EID: 26844556563     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11541868_21     Document Type: Conference Paper
Times cited : (9)

References (9)
  • 1
    • 8344253818 scopus 로고    scopus 로고
    • Federal Information Processing Standards Publication
    • National Institute of Standards and Technology: "Secure Hash Standard", Federal Information Processing Standards Publication 180-2, 2002.
    • (2002) Secure Hash Standard , pp. 180-182
  • 3
    • 26844543235 scopus 로고    scopus 로고
    • Verification of a cryptographic circuit: SHA-1 using ACL2
    • Austin, USA
    • D. Toma, D. Borrione: "Verification of a cryptographic circuit: SHA-1 using ACL2", ACL2 Workshop, Austin, USA, 2004.
    • (2004) ACL2 Workshop
    • Toma, D.1    Borrione, D.2
  • 5
    • 24144471794 scopus 로고    scopus 로고
    • Combining several paradigms for circuit validation and verification
    • Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
    • D. Toma, D. Borrione, G. Al-Sammane: "Combining several paradigms for circuit validation and verification", in Construction and Analysis of Safe, Secure, and Interoperable Smart Devices, LNCS, Vol 3362/2005, pp. 229.
    • LNCS , vol.3362 , Issue.2005 , pp. 229
    • Toma, D.1    Borrione, D.2    Al-Sammane, G.3
  • 7
    • 84856140605 scopus 로고    scopus 로고
    • Verification of synchronous sequential machines based on symbolic execution
    • Automatic Verification Methods for Finite State Systems, Springer
    • O. Coudert, C. Berthet, J.C. Madre: "Verification of synchronous sequential machines based on symbolic execution", in Automatic Verification Methods for Finite State Systems, LNCS No407, Springer, pp.365-373.
    • LNCS No407 , vol.407 , pp. 365-373
    • Coudert, O.1    Berthet, C.2    Madre, J.C.3
  • 8
    • 84937570704 scopus 로고    scopus 로고
    • Modeling and verifying systems using a logic of counter arithmetic with lambda expressions and uninterpreted functions
    • Computer Aided Verification
    • R. E. Bryant, S. K. Lahiri, S. A. Seshia: "Modeling and Verifying Systems using a Logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions", in Computer Aided Verification, LNCS 2404, pp. 78-99, 2002.
    • (2002) LNCS , vol.2404 , pp. 78-99
    • Bryant, R.E.1    Lahiri, S.K.2    Seshia, S.A.3
  • 9
    • 84958753231 scopus 로고    scopus 로고
    • EVC: A validity checker for the logic of equality with uninterpreted functions and memories, exploiting positive equality and conservative transformations
    • Computer Aided Verification
    • M. N. Velev, R. E. Bryant: "EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality and Conservative Transformations", in Computer Aided Verification, LNCS 2102, 2001.
    • (2001) LNCS , vol.2102
    • Velev, M.N.1    Bryant, R.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.