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Volumn 3362, Issue , 2005, Pages 229-249

Combining several paradigms for circuit validation and verification

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CRYPTOGRAPHY; SPECIFICATIONS; TRANSFER FUNCTIONS;

EID: 24144471794     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/978-3-540-30569-9_12     Document Type: Conference Paper
Times cited : (4)

References (20)
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    • W. Roesner: "What Is Beyond The RTL Horizon for Microprocessor and System Design?", Keynote, CHARME'03, L'Aquila, Italy, 21-24 October 2003.
    • (2003) CHARME'03
    • Roesner, W.1
  • 6
    • 84856140605 scopus 로고    scopus 로고
    • Verification of synchronous sequential machines based on symbolic execution
    • Automatic Verification Methods for Finite State Systems, Springer
    • O. Coudert, C. Berthet, J.C. Madre: "Verification of synchronous sequential machines based on symbolic execution", in Automatic Verification Methods for Finite State Systems, Lecture Notes in Computer Science No407, Springer, pp.365-373.
    • Lecture Notes in Computer Science No407 , vol.407 , pp. 365-373
    • Coudert, O.1    Berthet, C.2    Madre, J.C.3
  • 12
    • 0034290057 scopus 로고    scopus 로고
    • A compositional model for the functional verification of high-level synthesis results
    • Oct.
    • D. Borrione, J. Dushina, L. Pierre: "A Compositional Model for the Functional Verification of High-level Synthesis Results", IEEE. Trans. on VLSI, Vol8, No5, Oct. 2000, pp. 526-530.
    • (2000) IEEE. Trans. on VLSI , vol.8 , Issue.5 , pp. 526-530
    • Borrione, D.1    Dushina, J.2    Pierre, L.3
  • 13
    • 0018307925 scopus 로고
    • Application of program verification techniques to hardware verification
    • J. Darringer. "Application of Program Verification Techniques to Hardware Verification". In Proc. IEEE-ACM Design Automation Conference, pp. 375-381, 1979.
    • (1979) Proc. IEEE-ACM Design Automation Conference , pp. 375-381
    • Darringer, J.1
  • 14
    • 0001510331 scopus 로고
    • Formal verifcation by symbolic evaluation of partially-ordered trajectories
    • March
    • R. E. Bryant and C. J. H. Seger. "Formal Verifcation by Symbolic Evaluation of Partially-ordered Trajectories". Formal Methods in System Design, 6(2):pp. 147-189, March 1995.
    • (1995) Formal Methods in System Design , vol.6 , Issue.2 , pp. 147-189
    • Bryant, R.E.1    Seger, C.J.H.2
  • 15
    • 84948166044 scopus 로고    scopus 로고
    • Generalized symbolic trajectory evaluation abstraction in action
    • Proc. FMCAD, Portland, USA, Nov
    • J. Yang and C.I. Seger. "Generalized Symbolic Trajectory Evaluation Abstraction in Action". Proc. FMCAD, Portland, USA, Nov 2002. Springer LNCS 2517, pp. 70-87.
    • (2002) Springer LNCS , vol.2517 , pp. 70-87
    • Yang, J.1    Seger, C.I.2
  • 16
    • 84948977029 scopus 로고    scopus 로고
    • Symbolic simulation of the JEM1 microprocessor
    • Proc. FMCAD'98, Palo Alto, CA
    • D. Greve. "Symbolic Simulation of the JEM1 Microprocessor". Proc. FMCAD'98, Palo Alto, CA, 1998. Springer LNCS 1522, pp. 321-333.
    • (1998) Springer LNCS , vol.1522 , pp. 321-333
    • Greve, D.1
  • 18
    • 84948970435 scopus 로고    scopus 로고
    • Symbolic simulation: An ACL2 approach
    • Proc. FMCAD'98, Palo Alto, CA
    • J. S. Moore. "Symbolic Simulation: An ACL2 Approach." Proc. FMCAD'98, Palo Alto, CA, 1998. Springer LNCS 1522, pp. 334-350.
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    • Moore, J.S.1
  • 20
    • 33645595777 scopus 로고    scopus 로고
    • Formai validation of high level specification of data-path digital circuits by symbolic simulation
    • Poznan, Poland, April
    • G. Al Sammane, D. Borrione: "Formai Validation of High Level Specification of Data-path Digital Circuits by Symbolic Simulation" Proc. DDECS'03, Poznan, Poland, April 2003.
    • (2003) Proc. DDECS'03
    • Al Sammane, G.1    Borrione, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.