Verification of synchronous sequential machines based on symbolic execution

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 407 LNCS, Issue , 1990, Pages 365-373

  Coudert, Olivier ^a   Berthet, Christian ^a   Madre, Jean Christophe ^a  

^a BULL Research Center ^*  (France)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS;

BREADTH-FIRST TRAVERSAL; DECISION GRAPHS; STATE ENUMERATION; SYMBOLIC EXECUTION; SYMBOLIC EXPRESSION;

SEQUENTIAL MACHINES;

EID: 84856140605     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-52148-8_30     Document Type: Conference Paper

References (14)

1. F. Anceau, "Design Methodology for Large Custom Processors". Proc. of the 1986 ESSIR Conference, Delft.
2. J. R. Armstrong, Chip-Level Modeling with VHDL, Prentice Hall, 1989.
3. J. P. Billon, "Perfect Normal Forms for Discrete Functions", BULL Research Report N°87019, June 1987.
4. J. P. Billon, J. C. Madre, "Original Concepts of PRIAM, an Industrial Tool for Efficient Formal Verification of Combinational Circuits", in The Fusion of Hardware Design and Verification, G. J. Milne Editor, North Holland, 1988.
5. O. Coudert, J. C. Madre, "Logics over Finite Domain of Interpretation: Proof and Resolution Procedures", BULL Research Report to appear, 1989.
6. S. Devadas, H. K. Ma, R. Newton, "On the Verification of Sequential Machines at Differing Levels of Abstraction", IEEE Transactions on CAD, Vol. 7, No. 6,1988.
7. D. Dietmeyer, Logic Design of Digital Systems, Allyn & Bacon, 2nd edition, 1978.
8. J. E. Hopcroft, J. D. Ullman, Introduction to Automata Theory, Langages and Computation, Addison-Wesley, Reading, Mass., 1979.
9. S. H. Hwang, A. R. Newton, "An efficient Design Correctness Checker of Finite State Machines", ICCAD 1987.
10. D. Jaillet, P. Mertens, IDS Reference Manual, BULL S.A., May 1987.
11. J. C. Madre, J. P. Billon, "Proving Circuit Correctness using Formal Comparison Between Expected and Extracted Behaviour", Proc. of the 25th Design Automation Conference, 1988.
12. J. C. Madre, O. Coudert, "Formal Verification of Digital Circuits Using a Propositional Theorem Prover", IFIP Working Conference on the CAD Systems Using AI Techniques, June 1989.
13. J. Y. Murzin, "FAON A functional Abstractor of Netlist", Actes du Séminaire de Programmation Logique, Lannion, France, 1986.
14. K. J. Supowit, S. J. Friedman, "A new Method for Verifying Sequential Circuits", Proc. of the 23rd Design Automation Conference, 1986.