From PSL to LTL: A formal validation in HOL

Lecture Notes in Computer Science

Volumn 3603, Issue , 2005, Pages 342-357

  Tuerk, Thomas ^a   Schneider, Klaus ^a  

^a University of Koblenz Landau   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ACCIDENT PREVENTION; AUTOMATA THEORY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FORMAL LOGIC; MATHEMATICAL MODELS; SPECIFICATIONS;

ACCELLERA'S PROPERTY; HOL THEOREM PROVERS; LOGIC HIERARCHY; LTL;

THEOREM PROVING;

EID: 26844554917     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11541868_22     Document Type: Conference Paper

References (33)

1. ACCELLERA. Property specification language reference manual, version 1.1. http://www.eda.org, June 2004.
2. ANSI/IEEE STD 1076-1987. IEEE Standard VHDL Language Reference Manual. New York, USA, March 1987.
3. ARMONI, R., BUSTAN, D., KUPFERMAN, O., AND VARDI, M. Resets vs. aborts in linear temporal logic. In Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS) (Warsaw, Poland, 2003), H. Garavel and J. Hatcliff, Eds., vol. 2619 of LNCS, Springer, pp. 65-80.
4. ARMONI, R., FIX, L., FLAISHER, A., GERTH, R., GINSBURG, B., KANZA, T., LANDVER, A., MADOR-HAIM, S., SINGERMAN, E., TIEMEYER, A., VARDI, M., AND ZBAR, Y. The ForSpec temporal logic: A new temporal property-specification language. In Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS) (Grenoble, France, 2002), J.-P. Katoen and P. Stevens, Eds., vol. 2280 of LNCS, Springer, pp. 296-211.
5. BEER, I., BEN-DAVID, S., EISNER, C., FISMAN, D., GRINGAUZE, A., AND RODEH, Y. The temporal logic Sugar. In Conference on Computer Aided Verification (CAV) (Paris, France, 2001), vol. 2102 of LNCS, Springer, pp. 363-367.
6. CHANG, K.-H., Tu, W.-T., YEH, Y.-J., AND Kuo, S.-Y. A temporal assertion extension to Verilog. In International Symposium on Automated Technology for Verification and Analysis (ATVA) (2004), vol. 3299 of LNCS, Springer, pp. 499-504.
7. CLARKE, E., EMERSON, E., AND SISTLA, A. Automatic verification of finite-state concurrent systems using temporal logic specifications. ACM Transactions on Programming Languages and Systems (TOPLAS) 8, 2 (April 1986), 244-263.
8. DANIELE, M., GIUNCHIGLIA, F., AND VARDI, M. Improved automata generation for linear temporal logic. In Conference on Computer Aided Verification (CAV) (Trento, Italy, 1999), N. Halbwachs and D. Peled, Eds., vol. 1633 of LNCS, Springer, pp.249-260.
9. EMERSON, E., AND CLARKE, E. Using branching-time temporal logic to synthesize synchronization skeletons. Science of Computer Programming 2, 3 (1982), 241-266.
10. EMERSON, E., AND LEI, C.-L. Modalities for model checking: Branching time strikes back. Science of Computer Programming 8 (1987), 275-306.
11. GABBAY, D., PNUELI, A., SHELAH, S., AND STAVI, J. On the temporal analysis of fairness. In Symposium on Principles of Programming Languages (POPL) (New York, 1980), ACM, pp. 163-173.
12. GASTIN, P., AND ODDOUX, D. Fast LTL to Büchi automata translation. In Conference on Computer Aided Verification (CAV) (Paris, France, 2001), vol. 2102 of LNCS, Springer, pp. 53-65.
13. GERTH, R., PELED, D., VARDI, M., AND WOLPER, P. Simple on-the-fly automatic verification of linear temporal logic. In Protocol Specification, Testing, and Verification (PSTV) (Warsaw, June 1995), North Holland.
14. GORDON, M. PSL semantics in higher order logic. In Workshop on Designing Correct Circuits (DCC) (Barcelona, Spain, 2004).
15. HAVLICEK, J., FISMAN, D., AND EISNER, C. Basic results on the semantics of Accellera PSL 1.1 foundation language. Technical Report 2004.02, Accellera, 2004.
16. KLEENE, S. Representation of events in nerve nets and finite automata. In Automata Studies, C. Shannon and J. McCarthy, Eds. Princeton University Press, Princeton, NJ, 1956, pp. 3-41.
17. LANDWEBER, L. Decision problems for ω-automata. Mathematical Systems Theory 3, 4 (1969), 376-384.
18. MANNA, Z., AND PNUELI, A. A hierarchy of temporal properties. In Symposium on Principles of Distributed Computing (1990), pp. 377-408.
19. MARKEY, N. Temporal logic with past is exponentially more succinct. Bulletin of the European Association for Theoretical Computer Science 79 (2003), 122-128.
20. MCNAUGHTON, R., AND PAPERT, S. Counter-free Automata. MIT, 1971.
21. MOORBY, P. History of Verilog. IEEE Design and Test of Computers (September 1992), 62-63.
22. PNUELI, A. The temporal logic of programs. In Symposium on Foundations of Computer Science (FOCS) (New York, 1977), vol. 18, IEEE Computer Society, pp. 46-57.
23. REETZ, R., SCHNEIDER, K., AND KROPF, T. Formal specification in VHDL for formal hardware verification. In Design, Automation and Test in Europe (DATE) (February 1998), IEEE Computer Society.
24. SCHNEIDER, K. Improving automata generation for linear temporal logic by considering the automata hierarchy. In Logic for Programming, Artificial Intelligence, and Reasoning (LPAR) (Havanna, Cuba, 2001), vol. 2250 of LNAI, Springer, pp. 39-54.
25. SCHNEIDER, K. Verification of Reactive Systems - Formal Methods and Algorithms. Texts in Theoretical Computer Science (EATCS Series). Springer, 2003.
26. SCHNEIDER, K., AND HOFFMANN, D. A HOL conversion for translating linear time temporal logic to omega-automata. In Higher Order Logic Theorem Proving and its Applications (TPHOL) (Nice, France, 1999), Y. Bertot, G. Dowek, A. Hirschowitz, C. Paulin, and L. Théry, Eds., vol. 1690 of LNCS, Springer, pp. 255-272.
27. SCHUELE, T., AND SCHNEIDER, K. Bounded model checking of infinite state systems: Exploiting the automata hierarchy. In Formal Methods and Models for Code-sign (MEMOCODE) (San Diego, CA, June 2004), IEEE, pp. 17-26.
28. SOMENZI, F., AND BLOEM, R. Efficient Büchi automata from LTL formulae. In Conference on Computer Aided Verification (CAV) (Chicago, IL, USA, 2000), E. Emerson and A. Sistla, Eds., vol. 1855 of LNCS, Springer, pp. 248-263.
29. THOMAS, W. Automata on Infinite Objects, vol. B. Elsevier, 1990, ch. Automata on Infinite Objects, pp. 133-191.
30. IEEE Standard VHDL Language Reference Manual. New York, USA, June 1993. ANSI/IEEE Std 1076-1993.
31. WAGNER, K. On ω-regular sets. Information and Control 43 (1979), 123-177.
32. WOLPER, P. Temporal logic can be more expressive. In Symposium on Foundations of Computer Science (FOCS) (New York, 1981), IEEE Computer Society, pp. 340-348.
33. WOLPER, P., VARDI, M., AND SISTLA, A. Reasoning about infinite computations paths. In Symposium on Foundations of Computer Science (FOCS) (New York, 1983), IEEE Computer Society, pp. 185-194.