A Temporal Assertion Extension to Verilog

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3299, Issue , 2004, Pages 499-504

  Chang, Kai Hui ^a   Tu, Wei Ting ^a   Yeh, Yi Jong ^a   Kuo, Sy Yen ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

PSL; Temporal assertion; Verification

Indexed keywords

COMPUTERS; VERIFICATION;

CIRCUIT DESIGNS; PSL; TEMPORAL ASSERTION; TEMPORAL RULES; TEST-BENCH;

ARTIFICIAL INTELLIGENCE;

EID: 26844565409     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30476-0_45     Document Type: Article

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