A new 40-nm SONOS structure based on backside trapping for nanoscale memories

IEEE Transactions on Nanotechnology

Volumn 4, Issue 5, 2005, Pages 581-586

  Ranica, Rossella ^b   Villaret, Alexandre ^b   Mazoyer, Pascale ^b,e   Monfray, Stephane ^b,f   Chanemougame, Daniel ^b   Masson, Pascal ^c,g,h,i   Regnier, Arnaud ^c   Dray, Cyrille N ^b   Bez, Roberto ^d,j,k,l,m   Skotnicki, Thomas ^a,b  

^a IEEE

^b STMICROELECTRONICS   (France)

^c CNRS   (France)

^d STMICROELECTRONICS   (Italy)

^e AIX MARSEILLE UNIVERSITY   (France)

^f SON Project

^g AIX MARSEILLE UNIVERSITÉ   (France)

^h New Memories on Silicon ^*  (United Kingdom)

ⁱ New Memories on Silicon (MISSi) Group

^j UNIVERSITY OF MILAN   (Italy)

^k UNIVERSITY OF PADOVA   (Italy)

^l UNIVERSITY OF UDINE   (Italy)

^m International Electron Device Meeting Technical Subcommittee

more..

Author keywords

Charge trapping; CMOS integrated memories; Nitride traps; Nonvolatile memories (NVMs); Silicon oxide nitride oxide silicon (SONOS) memory

Indexed keywords

CHARGE TRAPPING; CMOS INTEGRATED MEMORIES; NITRIDE TRAPS; NONVOLATILE MEMORIES (NVMS); SILICON-OXIDE-NITRIDE-OXIDE-SILICON (SONOS) MEMORY;

CMOS INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; ELECTRIC BATTERIES; ELECTRIC CHARGE; MOS DEVICES; NANOTECHNOLOGY; THRESHOLD VOLTAGE;

SILICON;

EID: 26644474125     PISSN: 1536125X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNANO.2005.851416     Document Type: Article

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