Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs

Microelectronic Engineering

Volumn 73-74, Issue , 2004, Pages 346-350

  Lemme, M C ^a   Mollenhauer, T ^a   Gottlob, H ^a   Henschel, W ^a   Efavi, J ^a   Welch, C ^b   Kurz, H ^a  

^a AMO GMBH   (Germany)

^b OXFORD INSTRUMENTS PLASMA TECHNOLOGY   (United Kingdom)

Author keywords

FinFET; HBr; SOI; Triple Gate MOSFET

Indexed keywords

ANISOTROPY; ETCHING; GATES (TRANSISTOR); MOSFET DEVICES; NANOSTRUCTURED MATERIALS; OXYGEN; POLYSILICON; SILICA; SILICON ON INSULATOR TECHNOLOGY; SILICON WAFERS;

FINFET; HBR; SOI; TRIPLE-GATE MOSFET;

MICROELECTRONICS;

EID: 2542489737     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(04)00123-6     Document Type: Conference Paper

References (5)

1. International Technology Roadmap for Semiconductors: 2002 Update, International Sematech, Available from 〈 http://public.itrs.net/Files/ 2002Update/2002Update.pdf〉, 2002.
2. Wong H.P., Frank D.J., Solomon P.M., Wann C.H., Welser J.J. Proc. IEEE. 87(4):1999;537-569.
3. Choi Y.-K., King T.-J., Hu C. IEEE Electron Dev. Lett. 23(1):2002;25-27.
4. Lemme M., Mollenhauer T., Henschel W., Wahlbrink T., Heuser M., Baus M., Winkler O., Spangenberg B., Granzner R., Schwierz F., Kurz H. Microelectron. Eng. 67-68:2003;810-817.
5. Maile B.E., Henschel W., Kurz H., Rienks B., Polman R., Kaars O. Jpn. J. Appl. Phys. 39:2000;6836-6842.