Process-window sensitive full-chip inspection for design-to-silicon optimization in the sub-wavelength era

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5756, Issue , 2005, Pages 51-60

  Brodsky, MaryJane ^a   Halle, Scott ^a   Jophlin Gut, Vickie ^a   Liebmann, Lars ^a   Samuels, Don ^a   Crispo, Gary ^b   Nafisi, Kourosh ^b   Ramani, Vijay ^b   Peterson, Ingrid ^b  

^a IBM MICROELECTRONICS   (United States)

^b KLA TENCOR CORPORATION   (United States)

Author keywords

Brightfield imaging wafer inspection techniques; Design for Manufacturing; Process window verification and qualification

Indexed keywords

CMOS INTEGRATED CIRCUITS; ERRORS; MATHEMATICAL MODELS; OPTICAL RESOLVING POWER; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

BRIGHTFIELD IMAGING WAFER INSPECTION TECHNIQUES; DESIGN FOR MANUFACTURING (DFM); IMAGING INSPECTION TECHNOLOGY; PROCESS WINDOW VERIFICATION AND QUALIFICATION;

PHOTOLITHOGRAPHY;

EID: 25144465962     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.599865     Document Type: Conference Paper

References (3)

1. Chris M. Jones, et. al., "Faster qualification of 193-nm resists for 100-nm development using photo cellmonitoring", SPIE Microlithography, 2003.
2. L. Liebmann et al., "High-performance circuit design for the RET-enabled 65 nm technology node." Design and Process Integration for Microcelectronic Manufacturing III, SPIE 5379, 2004
3. L. Liebmann, S. Mansfield. J. Bruce, M. Cross. I. Graur, A. McGuire, J. Krueger, D. Sunderling, "Optimizing style options for sub-resolution assist features," in Proc. SPIE (C. Progler, ed.). vol 4346, SPIE, 2001.