Comparison of thin film cracking and delamination for aluminum and copper silicon interconnects with organic packaging

Proceedings - Electronic Components and Technology Conference

Volumn 1, Issue , 2005, Pages 349-355

  He, Dongming ^a   Zhang, Charles ^a   Chiang, Daniel ^a   Zheng, Tieyu ^a   Lucero, Alan ^a   Stage, Roger ^a   Atluri, Vasu ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALUMINUM; CRACK INITIATION; DELAMINATION; ELECTRONICS PACKAGING; SILICON; THIN FILMS;

COPPER DAMASCENE; INTERCONNECT TECHNOLOGIES; THERMAL EXPANSION MISMATCH; THIN FILM CRACKING;

OPTICAL INTERCONNECTS;

EID: 24644515954     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. Stephen A. Gee et al., "A test chip design for detecting thin film cracking in integrated circuits", IEEE Transactions on Components, Packaging, and Manufacturing Technology - Part B, Vol.18, No.3, August, 1995, pp.478-484.
3. Mark Bohr et al., "A high performance 0.25 μm logic technology optimized for 1.8V operation", IEDM Tech. Dig., pp.847-850, 1996.
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5. Sunit Tyagi et al., "A 130 nm generation logic technology featuring 70 nm transistors, daual Vt transistors and 6 layers of Cu interconnects", IEDM Tech. Dig., pp.567-570, 2000.
6. Scott Thompson et al., "130 nm logic technology featuring 60 nm transistors, low-K dielectrics, and Cu Interconnects", Intel Technology Journal Vol. 6 Issue 2, pp.5-13.
7. Kuo-Yu Chou et al., "Die cracking evaluation and improvement in ULSI plastic package", Proceedings of 2001 IEEE Int. Conference on Microelectronics Test Structures, pp.239-244.