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Volumn , Issue , 2005, Pages 88-93

Multiple-valued logic approach for a systolic AB2 circuit in galois field

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; ERROR CORRECTION; PUBLIC KEY CRYPTOGRAPHY;

EID: 24644445509     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (3)

References (8)
  • 5
    • 0242578167 scopus 로고    scopus 로고
    • Constructing composite field representations for efficient conversion
    • Nov.
    • B. Sunar, E. Savas, C. K. Koc, "Constructing composite field representations for efficient conversion, " IEEE Transactions on computers, Volume 52, Issue 11, Nov. 2003, pp. 1391-1398.
    • (2003) IEEE Transactions on Computers , vol.52 , Issue.11 , pp. 1391-1398
    • Sunar, B.1    Savas, E.2    Koc, C.K.3
  • 6
    • 0027568593 scopus 로고
    • Neuron MOS voltage-mode circuit technology for multiple-valued logic
    • March
    • T. Shibata, and T. Ohmi, "Neuron MOS voltage-mode circuit technology for multiple-valued logic, " IEICE Trans. Electronics, Vol. E76-C, No. 3, March 1993, pp. 347-356.
    • (1993) IEICE Trans. Electronics , vol.E76-C , Issue.3 , pp. 347-356
    • Shibata, T.1    Ohmi, T.2
  • 7
    • 0242575828 scopus 로고    scopus 로고
    • Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETs
    • October
    • A. Srivastava, and H. N. Venkata, "Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETs, " Integration, the VLSI Journal, Vol. 36, Issue 3, October 2003, pp. 87-101.
    • (2003) Integration, the VLSI Journal , vol.36 , Issue.3 , pp. 87-101
    • Srivastava, A.1    Venkata, H.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.