Quaternary to binary bit conversion CMOS integrated circuit design using multiple-input floating gate MOSFETS

Integration, the VLSI Journal

Volumn 36, Issue 3, 2003, Pages 87-101

  Srivastava, Ashok ^a   Venkata, Harish N ^a  

^a LOUISIANA STATE UNIVERSITY   (United States)

Author keywords

CMOS; Floating gate MOSFET; MVL; Neuron MOSFET; Quaternary logic; VLSI design

Indexed keywords

BANDWIDTH; DIGITAL TO ANALOG CONVERSION; MOS CAPACITORS; MOSFET DEVICES; TRANSCEIVERS; TRANSISTORS; VLSI CIRCUITS;

BINARY BITS; QUATERNARY INPUTS;

CMOS INTEGRATED CIRCUITS;

EID: 0242575828     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(03)00049-X     Document Type: Article

References (15)

1. Butler J.T. Multiple-Valued Logic in VLSI. 1991;IEEE Computer Society Press Technology Series, Los Alamitos, CA.
2. S.L. Hurst, Two decades of multiple-valued logic - an invited tutorial, Proc. IEEE International Symposium on Multiple-Valued Logic, May 1998, p. 164.
3. Bryant R. Symbolic Boolean manipulation with ordered binary decision diagrams. ACM Computing Surveys. 24(3):1992;293-318.
4. Shanbhag N.R., Nagchoudhuri D., Siferd R.E., Vishweswaran G.S. Quaternary logic circuits in. 2 μ m CMOS technology IEEE J. Solid-State Circuits. 25:1990;790-799.
5. Razavi B. Design of Analog CMOS Integrated Circuits. 2001;McGraw-Hill, New York.
6. Mangin J.L., Current K.W. Characteristics of prototype CMOS quaternary logic encoder-decoder circuits. IEEE Trans. Comput. C-35:1986;157-161.
7. Current K.W. Current-mode multiple-valued logic circuits. IEEE J. Solid-State Circuits. 29:1994;95-107.
8. I.M. Thoidis, D. Soudris, I. Karafyllidis, A. Thanailakis, The design of low power multiple-valued logic encoder and decoder circuits, Proceedings of the Sixth IEEE International Conference on Electronics, Circuits and Systems, Vol. 3, September 1999, pp. 1623-1626.
9. T. Shibata, T. Ohmi, An intelligent MOS transistor featuring gate-level weighted sum and threshold operations, IEDM Tech. Dig. (1991) 919-922.
10. Shibata T., Ohmi T. A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Trans. Electron Dev. 39(6):1992;1444-1455.
11. Luck A., Jung S., Brederlow R., Thewes R., Goser K., Weber W. On the design robustness of threshold logic gates using multi-input floating gate MOS transistors. IEEE Trans. Electron Dev. 47:2000;1231-1239.
12. Weber W., Prange S.J., Thewes R., Wohlrab E., Luck A. On the application of the neuron MOS transistor principle for modern VLSI design. IEEE Trans. Electron Dev. 43:1996;1700-1708.
13. N. Weste, K. Eshraghian, Principles of CMOS VLSI Design - A Systems Perspective, Section 4.3.2, Addison-Wesley, Reading, MA, 1988, p. 125.
14. Srivastava A., Venkata H.N., Ajmera P.K. A novel scheme for a higher bandwidth sensor readout. Proc. SPIE. 4700:2002;17-28.
15. H.N. Venkata, Ternary and quaternary logic to binary bit conversion CMOS integrated circuit design using multiple input floating gate MOSFETs, MS Thesis, Louisiana State University, Baton Rouge, December 2002.