Ternary systolic product-sum circuit for GF(3m) using neuron MOSFETs

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 1996, Pages 92-96

  Muranaka, Noriaki ^a   Arai, Shigenobu ^a   Imanishi, Shigeru ^a   Miller, D Michael ^a  

^a KANSAI UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; COMPUTER SIMULATION; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MANY VALUED LOGICS; MOSFET DEVICES; MULTIPLYING CIRCUITS; PIPELINE PROCESSING SYSTEMS; SYSTOLIC ARRAYS;

BINARY CIRCUIT; GATE ELECTRODE; NEURON MOSFETS; PRODUCT SUM COMPUTATION CIRCUIT; TERNARY CIRCUIT; THRESHOLD VOLTAGE; VOLTAGE MODE NEURON;

LOGIC CIRCUITS;

EID: 0029695158     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)