Computation of AB2 multiplication in GF(2m) using low-complexity systolic architecture

IEE Proceedings: Circuits, Devices and Systems

Volumn 150, Issue 2, 2003, Pages 119-123

  Kim, N Y ^a   Kim, H S ^b   Yoo, K Y ^a  

^a Kyungpook National University   (South Korea)

^b Kyungil University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DATA PROCESSING; DIGITAL SIGNAL PROCESSING; MICROPROCESSOR CHIPS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

HIGH-SPEED CIRCUITS;

CRYPTOGRAPHY;

EID: 0037982780     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20030337     Document Type: Article

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