A 0.13μm triple-Vt 9MB third level on-die cache for the Itanium® 2 processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Chang, Jonathan ^a   Shoemaker, Jonathan ^a   Haque, Mizan ^a   Huang, Ming ^a   Truong, Kevin ^a   Karim, Mesbah ^a   Chiu, Siufu ^a   Leong, Gloria ^a   Desai, Kiran ^a   Goe, Richard ^a   Kulkarni, Sandhya ^a   Rao, Arun ^a   Hannoun, Daniel ^a   Rusu, Stefan ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE DATA ARRAYS; ROUTING; SUBARRAYS;

BANDWIDTH; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DATA TRANSFER; DIELECTRIC MATERIALS; ELECTRIC NETWORK ANALYSIS; FIELD EFFECT TRANSISTORS; ROUTERS;

PROGRAM PROCESSORS;

EID: 2442675670     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. Thompson et al, "An Enhanced 130nm Generation Logic Technology Featuring 60nm Transistors Optimized for High Performance and Low Power," IEDM Tech. Digest, pp 257-260, Dec. 2001.
2. J. Stinson, S. Rusu, "A 1.5GHz Third Generation Itanium® Processor," ISSCC Dig. Tech. Papers, pp 252-253, Feb. 2003.
3. D. Weiss et al, "The On-Chip 3MB Subarray Based 3rd Level Cache on an Itanium® Microprocessor," ISSCC Dig. Tech. Papers, pp 112-113, Feb. 2002.
4. A. Bhavnagarwala et al., "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE J. Solid-State Circuits, pp 658-665, Apr. 2001.