NSGA-based parasitic-aware optimization of a 5GHz low-noise VCO

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 169-174

  Chu, Min ^a   Allstot, David J ^a   Huard, Jeffrey M ^b   Wong, Kim Y ^b  

^a University of Washington   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATORS; NON-DOMINATED SORTING GENETIC ALGORITHM (NSGA); PARETO OPTIMAL FRONT; RF CIRCUITS;

CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; COMPUTATIONAL METHODS; COMPUTER SIMULATION; GENETIC ALGORITHMS; MONTE CARLO METHODS; OPTIMIZATION; SIMULATED ANNEALING;

VARIABLE FREQUENCY OSCILLATORS;

EID: 2442626715     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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