Automatic analog layout retargeting for new processes and device sizes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2003, Pages

  Jangkrajarng, Nuttorn ^a   Bhattacharya, Sambuddha ^a   Hartono, Roy ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; LINEAR PROGRAMMING; MOS CAPACITORS; MOSFET DEVICES; OPERATIONAL AMPLIFIERS; PROBLEM SOLVING;

RESIZING TOOLS;

INTEGRATED CIRCUIT LAYOUT;

EID: 0038419531     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. K. Ousterhout, "Comer stitching: A Data-Structuring Technique for VLSI Layout Tools", IEEE Transactions on Computer Aided-Design of Integrated Circuits and Systems, pp.87-100, January 1984.
2. S. L. Lin and J. Allen, "Minplex - A Compactor that Minimizes the Bounding Rectangle and Individual Rectangles in a Layout". Proceedings of Design Automation Conference, pp.123-130, 1986.
3. Y. Bourai and C. J. R. Shi, "Symmetry Detection for Automatic Analog Layout Recycling", Proceedings of Asian and South Pacific Design Automation Conference, pp.5-8,1999.
4. R. Okuda, T. Sato, H. Onedera and K. Tamaru, "An Efficient Algorithm for Layout Compaction Problem with Symmetry Constraints", Proceedings of International Conf. on Computer Aided Design, pp.148-151, Nov. 1989.
5. G. Lakhani and R. Varadarajan, "A Wire-Length Minimization Algorithm for Circuit Layout Compaction", Proceedings of International Symposium on Circuits and Systems, pp.276-279, 1987.
6. T. H. Cormen, C. E. Leiserson and R. L, Rivest, Introduction to Algorithms MIT Press, 1990.