Twin SONOS memory with 30-nm storage nodes under a merged gate fabricated with inverted sidewall and damascene process

IEEE Electron Device Letters

Volumn 25, Issue 5, 2004, Pages 317-319

  Lee, Yong Kyu ^a   Song, Ki Whan ^a   Hyun, Jae Woong ^a   Lee, Jong Duk ^a   Park, Byung Gook ^a   Kang, Sung Taeg ^b   Choe, Jeong Dong ^b   Han, Sang Yeon ^b   Han, Jeong Nam ^b   Lee, Sung Woo ^b   Kwon, O Ik ^b   Chung, Chilhee ^b   Park, Donggun ^b   Kim, Kinam ^b  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

2 bit; Endurance; Flash; Inverted sidewall pattern (ISP); Multi; ONO; Retention; Silicon oxide nitride oxide Silicon (SONOS); Twin

Indexed keywords

AMORPHOUS SILICON; DIFFUSION; DURABILITY; ELECTRON DEVICE MANUFACTURE; GATES (TRANSISTOR); NITRIDES; OXIDES; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING SILICON; TRANSMISSION ELECTRON MICROSCOPY;

CHARGE DISTRIBUTION; DAMASCENE GATE PROCESS; INVERTED SIDEWALL PATTERNING METHOD; MEMORY CELL; SILICON OXIDE NITRIDE OXIDE SILICON FLASH MEMORY;

FLASH MEMORY;

EID: 2442480714     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.826535     Document Type: Letter

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