-
1
-
-
0029409963
-
A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS
-
C. Jansson A high-resolution, compact, and low-power ADC suitable for array implementation in standard CMOS IEEE Trans. Circuits Syst.-I 42 11 1995 904 912
-
(1995)
IEEE Trans. Circuits Syst.-I
, vol.42
, Issue.11
, pp. 904-912
-
-
Jansson, C.1
-
2
-
-
2542523967
-
Theory and applications of incremental Delta Sigma converters
-
J. Markus, J. Silva, and G.C. Temes Theory and applications of incremental Delta Sigma converters IEEE Trans. Circuits Syst.-I 51 4 2004 678 690
-
(2004)
IEEE Trans. Circuits Syst.-I
, vol.51
, Issue.4
, pp. 678-690
-
-
Markus, J.1
Silva, J.2
Temes, G.C.3
-
3
-
-
0035247571
-
A 13.5-bit 1.2 v micropower extended counting A/D converter
-
P. Rombouts, W. De Wilde, and L. Weyten A 13.5-bit 1.2 V micropower extended counting A/D converter IEEE J. Solid-State Circuits 36 2 2001 176 183
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, Issue.2
, pp. 176-183
-
-
Rombouts, P.1
De Wilde, W.2
Weyten, L.3
-
5
-
-
0023328711
-
A 16-bit low-voltage CMOS A/D converter
-
J. Robert, G.C. Temes, V. Valencic, R. Dessoulavy, and P. Deval A 16-bit low-voltage CMOS A/D converter IEEE J. Solid-State Circuits 22 2 1987 157 163
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, Issue.2
, pp. 157-163
-
-
Robert, J.1
Temes, G.C.2
Valencic, V.3
Dessoulavy, R.4
Deval, P.5
-
6
-
-
0027810431
-
Efficient circuit configurations for algorithmic analog to digital converters
-
K. Nagaraj Efficient circuit configurations for algorithmic analog to digital converters IEEE Trans Circuits Syst.-II Analog Digital Signal Process. 40 12 1993 777 785
-
(1993)
IEEE Trans Circuits Syst.-II: Analog Digital Signal Process.
, vol.40
, Issue.12
, pp. 777-785
-
-
Nagaraj, K.1
-
7
-
-
0032676910
-
MOSFET-only switched-capacitor circuits in digital CMOS technology
-
H. Yoshizawa, P. Ferguson, and G. Temes MOSFET-only switched-capacitor circuits in digital CMOS technology IEEE J. Solid-State Circuits 34 6 1999 734 747
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.6
, pp. 734-747
-
-
Yoshizawa, H.1
Ferguson, P.2
Temes, G.3
-
8
-
-
0033893576
-
Digital cancellation of D/A converter noise in pipelined A/D converters
-
I. Galton Digital cancellation of D/A converter noise in pipelined A/D converters IEEE Trans. Circuits Syst.-I 47 3 2000 185 196
-
(2000)
IEEE Trans. Circuits Syst.-I
, vol.47
, Issue.3
, pp. 185-196
-
-
Galton, I.1
-
9
-
-
0348233280
-
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
-
B. Murmann, and B.E. Boser A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification IEEE J. Solid-State Circuits 38 12 2003 2040 2050
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, Issue.12
, pp. 2040-2050
-
-
Murmann, B.1
Boser, B.E.2
-
10
-
-
0025386508
-
A high-swing high-impedance MOS cascode circuit
-
E. Sackinger, and W. Guggenbuhl A high-swing high-impedance MOS cascode circuit IEEE J. Solid-State Circuits 25 1 1990 289 298
-
(1990)
IEEE J. Solid-State Circuits
, vol.25
, Issue.1
, pp. 289-298
-
-
Sackinger, E.1
Guggenbuhl, W.2
-
11
-
-
0030286542
-
Circuit techniques for reducing the effects of opAmp imperfections: Autozeroing, correlated double sampling, and chopper stabilization
-
C. Enz, and G. Temes Circuit techniques for reducing the effects of opAmp imperfections autozeroing, correlated double sampling, and chopper stabilization Proceedings of The IEEE 84 11 November 1996 1584 1614
-
(1996)
Proceedings of the IEEE
, vol.84
, Issue.11
, pp. 1584-1614
-
-
Enz, C.1
Temes, G.2
-
12
-
-
0033349756
-
Circuit for the generation of balanced output signals
-
D. Baert Circuit for the generation of balanced output signals IEEE Trans. Instrum. Meas. 48 6 1999 1108 1110
-
(1999)
IEEE Trans. Instrum. Meas.
, vol.48
, Issue.6
, pp. 1108-1110
-
-
Baert, D.1
|