Modeling and Simulative Performance Analysis of SMP and Clustered Computer Architectures

Simulation

Volumn 74, Issue 2, 2000, Pages 84-96

  Burns, Mark W ^a   George, Alan D ^a   Wallace, Brad A ^a  

^a University of Florida   (United States)

Author keywords

architecture simulation; clusters; com puter modeling; parallel computers; Performance analysis

Indexed keywords

EID: 24144479858     PISSN: 00375497     EISSN: None     Source Type: Journal    
DOI: 10.1177/003754970007400203     Document Type: Article

References (24)

1. Zagar, M. and Basch, D. “Microprocessor Architecture Design with ATLAS.” IEEE Design & Test of Computers, Vol. 13, No. 3, pp 104-112, July-Sept. 1997.
2. Shanmugan, K.S., Frost, V.S. and LaRue, W. “A Block-Oriented Network Simulator (BONeS) “ SIMULATION, Vol. 58, No. 2, pp 83-94, Feb. 1992.
3. Dahlgren, Fredrik, “A Program-driven Simulation Model of an MIMD Multiprocessor” Proceedings of the 24th Annual Simulation Symposium, New Orleans, April 1991, pp 40-49.
4. Ayani, R., Ismailov, Y., Liljenstam, M., Popescu, A., Rajaei, H. and Rönngren, R. “Modeling and Simulation of a High Speed LAN.” SIMULATION, Vol. 64, No. 1, pp 7-13, Jan. 1995.
5. Edmondson, J. and Reilly, M. “Performance Simulation of an Alpha Microprocessor.” IEEE Computer, Vol. 31, No. 5, pp 50-58, May 1998.
6. McCarron, C.W. and Tung, C.-H. “Simulation Analysis of a Multiple Bus Shared Memory Multiprocessor.” SIMULATION, Vol. 61, No. 3, pp 169-175, Sept. 1993.
7. Poursepanj, A. “The Power PC Performance Modeling Methodology.” Communications of the ACM, Vol. 37, No. 6, pp 47-55, June 1994.
8. Qin, X. and Baer, J.-L. “A Performance Evaluation of Cluster Architectures” Proceedings of ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, Seattle, WA, June 15-18, 1997, pp 237-247.
9. Rosenblum, M. and Witchel, E. “Embra: Fast and Flexible Machine Simulation” Proceedings of ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, Philadelphia, May 23-26, 1996, pp 68-79.
10. Bose, P. and Conte, T.M. “Performance Analysis and Its Impact on Design.” IEEE Computer, Vol. 31, No. 5, pp 41-48, May 1998.
11. Rosenblum, M., Bugnion, E., Devine, S. and Herrod, S.A. “Using the SimOS Machine Simulator to Study Complex Computer Systems.” ACM Transactions on Modeling and Computer Simulation, Vol. 7, No. 1, pp 78-103, Jan. 1997.
12. George, A.D. “Simulating Microprocessor-Based Parallel Computers Using Processor Libraries.” SIMULATION, Vol. 60, No. 2, pp 129-134, Feb. 1993.
13. George, A.D. and Cook, Jr., S.W. “Distributed Simulation of Parallel DSP Architectures on Workstation Clusters.” SIMULATION, Vol. 67, No. 2, pp 94-105, Aug. 1996.
14. Dwarkadas, S., Jump, J.R. and Sinclair, J.B. “Execution-Driven Simulation of Multiprocessors: Address and Timing Analysis.” ACM Transactions on Modeling and Computer Simulation, Vol. 4, No. 4, pp 314-338, Oct. 1994.
15. Rosenblum, M., Herrod, S.A., Witchel, E. and Gupta, A. “Complete Computer System Simulation: The SimOS Approach.” IEEE Parallel and Distributed Technology, Vol. 3, No. 4, pp 34-43, Winter 1995.
16. Yan, Y., Zhang, X. and Ma, Q. “Software Support for Multiprocessor Latency Measurement and Evaluation.” IEEE Transactions on Software Engineering, Vol. 23, No. 1, pp 4-16, Jan. 1997.
17. Herrod, S.A. “Using Complete Machine Simulation to Understand Computer System Behavior.” Dissertation, Department of Computer Science, Stanford University, Feb. 1998.
18. Brewer, E.A., Dellarocas, C.N., Colbrook, A. and Weihl, W.E. “PROTEUS: A High-Performance Parallel-Architecture Simulator.” Technical Report TR-516, MIT/LCS, Laboratory for Computer Science, Cambridge, MA, Sept. 1991.
19. Bedichek, R.C. “Talisman: Fast and Accurate Multicomputer Simulation.” Proceedings of SIGMETRICS '95, Ottawa, Ontario, Canada, May 1995, pp 14-24.
20. George, A.D., Fogarty, R.B., Markwell, J.S. and Miars, M.D. “An Integrated Simulation Environment for Parallel and Distributed System Prototyping.” SIMULATION, Vol. 72, No. 5, pp 283-294, May 1999.
21. Hennessy, J.L. and Patterson, D.A. Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Francisco, Second Edition, 1995.
22. Kaeli, D.R. and Sailer, P.M. The DLX Instruction Set Architecture Handbook, Morgan Kaufmann, San Francisco, 1996.
23. IEEE Standard 1596-1992 Scalable Coherent Interface (SCI), IEEE Publications Office, 1-800-678-4333.
24. George, A.D., Phipps, W., Todd, R., Zirpoli, D., Justice, K., Giacoboni, M. and Sarwar, M. “SCI and the Scalable Cluster Architecture Latency-hiding Environment (SCALE) Project.” Proceedings of the 6th International SCI Workshop, Santa Clara, CA, Sept. 1996, pp 9-24.