Analysis and optimization of the back-gate effect on lateral high-voltage SOI devices

IEEE Transactions on Electron Devices

Volumn 52, Issue 7, 2005, Pages 1649-1655

  Schwantes, Stefan ^a   Florian, Tobias ^a   Stephan, Thilo ^a   Graf, Michael ^a   Dudek, Volker ^a  

^a Atmel Germany GmbH   (Germany)

Author keywords

High voltage; Lateral DMOS (LDMOS); Reduced surface field (RESURF) technology; Semiconductor device break down; Silicon insulator technology

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; GATES (TRANSISTOR); MATHEMATICAL MODELS; OPTIMIZATION; SILICON ON INSULATOR TECHNOLOGY;

HIGH VOLTAGE SOI DEVICES; LATERAL DMOS; REDUCED SURFACE FIELD (RESURF) TECHNOLOGY; SEMICONDUCTOR DEVICE BREAKDOWN;

MOSFET DEVICES;

EID: 23944478998     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2005.850952     Document Type: Article

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