Will moore's law be sufficient?

IEEE/ACM SC2004 Conference, Proceedings

Volumn , Issue , 2004, Pages 57-68

  DeBenedictis, Erik P ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPATIBILITY; MOORE'S LAW; SCIENTIFIC DISCOVERIES;

CODES (SYMBOLS); COMPUTER APPLICATIONS; COMPUTER SIMULATION; EXTRAPOLATION; MICROPROCESSOR CHIPS; ORDNANCE; PROBLEM SOLVING; SUPERCOMPUTERS;

LAWS AND LEGISLATION;

EID: 23944468220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (47)

1. [Anantharam 04] V. Anantharam, M. He, K. Natarajan, H. Xie, M. Frank, "Driving Fully-Adiabatic Logic Circuits Using Custom High-Q MEMS Resonators," 2004 workshop on Methodologies for Low Power Design, part of ESA '04 (Embedded Systems and Applications). Paper in PDF format at http://www.cise.ufl.edu/research/revcomp/AdiaMEMS/MLPD-04.pdf.
2. [Bennett 89] Charles H. Bennett, 'Time/Space Trade-Offs for Reversible Computation," SIAM Journal of Computing, Vol. 18, No. 4, pp. 766-776, August 1989.
3. [BGL web] IBM Blue Gene/L system, http://www.research.ibm.com/bluegene/.
4. [Brightwell 04] Ron Brightwell, William J. Camp, Ben Cole, Erik DeBenedictis, Robert W. Leland, "Architectural Specification for Massively Parallel Computers - An Experience and Measurement-Based Approach" To appear in Concurrency: Practice and Experience in 2004.
5. [Christopher 04a] Thomas W. Christopher, "Radiation Transport Algorithms on Trans-Petaflops Supercomputers of Different Architectures" Sandia National Laboratories Technical report SAND2003-2814, August 2003
6. [Christopher 04b] Thomas W. Christopher, "Pressures the Radiation Transport Problem Places on Future PIM-Based Supercomputer Designs," Workshop on Software for Processor-In-Memory Based Parallel Systems held in conjunction with the Second Annual IEEE/ACM International Symposium on Code Generation and Optimization, March 21, 2004.
7. [CTH web] Sandia maintains a Web site for the CTH program: http://www.cs.sandia.gov/departments/9232/cth/.
8. [Davis 04] Kei Davis, Adolfy Hoisie, Greg Johnson, Darren Kerbyson, Mike Lang, Scott Pakin, Fabrizio Petrini "Blue Gene: A Performance and Scalability Report at the 512-Processor Milestone, Los Alamos National Laboratories unlimited release technical report LA-UR- 04-1114.
9. [DeBenedictis 04a], Erik P. DeBenedictis, "Taking ASCI Supercomputing to the End Game," Sandia National Laboratories SAND report SAND2004-0959, March 2004. Sandia technical reports are available by going to http://www.sandia.gov and accessing the technical library.
10. [DeBenedictis 04b], Erik P. DeBenedictis, "Matching Supercomputing to Progress in Science," July 2004. Presentation at Lawrence Berkeley National Laboratory, also published as Sandia National Laboratories SAND report SAND2004-3333P. Sandia technical reports are available by going to http://www.sandia.gov and accessing the technical library.
11. [Denker 94] J. S. Denker. "A review of adiabatic computing," in 1994 IEEE Symposium on Low Power Electronics. Digest of Technical Papers, pp 94-97,1994.
12. [Drexler 92] Drexler, K. Eric., "Nanosystems: Molecular Machinery, Manufacturing, and Computation," John Wiley & Sons, Inc., 1992.
13. [Feynman 82] Richard P. Feynman, "Simulating Physics with Computers," International Journal of Theoretical Physics, Vol. 21. Nos. 6/7, 1982.
14. [Forsberg 03] Erik Forsberg, "Electronic and Photonic Quantum Devices," Doctoral Dissertation, Department of Microelectronics and Information Technology, Royal Institute of Technology Stockholm.
15. [Frank 97a] Michael P. Frank, "The R programming language and compiler." http://www.cise.ufl.edu/~mpf/rc/memos/M08/doc/doc.html.
16. [Frank 97b] Michael P. Frank, "Ultimate theoretical models of Nanocomputers," Nanotechnology 9 (1998) 162-176.
17. [Frank 99] Reversibility for Efficient Computing, Michael P. Frank, MIT Ph. D. thesis, 1999.
18. [Fredkin 82] E. Fredkin and T. Toffoli, "Conservative logic," International Journal of Theoretical Physics, vol. 21, no. 3/4, pp. 219-53, 1982.
19. [Han 02] Jie Hand and Pieter Jonker, "A System Architecture Solution for Unreliable Nanoelectronic Devices," IEEE Transactions on Nanotechnology Vol. 1, No. 4 (2002) 201-208.
20. [Hoisie 00] Adolfy Hoisie, Olaf Lubeck, Harvey Wasserman, "Performance and Scalability Analysis of Teraflop-Scale Parallel Architectures Using Multidimensional Wavefront Applications," in The International Journal of High Performance Computing Applications, Sage Science Press, Volume 14, Number 4, Winter 2000.
21. [IRAM 03] Overcoming the Limitations of Conventional Vector Processors", C. Kozyrakis, D. Patterson. 30th International Symposium on Computer Architecture, San Diego, CA, June 2003.
22. [ITRS 02] International Technology Roadmap for Semiconductors, http://public.itrs.net. All figures used in this report refer to the ITRS 2002 update.
23. [Jardin 03] S.C. Jardin, "Plasma Science Contribution to the SCaLeS Report," Princeton Plasma Physics Laboratory, PPPL-3879 UC-70, available on Internet.
24. [Kerbyson 01] Darren J. Kerbyson, Hank J. Alme, Adolfy Hoisie, Fabrizio Petrini, Harvey J. Wasserman, and Michael Gittings, "Predictive Performance and Scalability Modeling of a Large-Scale Application, in Proc. of IEEE/ACM SC2001, Denver, November 2001.
25. [Kim 01] Kim, S., Zeisler, C., Papaefthymiou, M., "A True Single-Phase 8-bit Àdiabatic Multiplier," in proceedings of the 2001 Design Automation Conference, pp. 758-763.
26. [Kung 82] Kung, H. T. "Why Systolic Architectures?," Computer, vol. 15, no. 1, pp. 37-46, 1982.
27. [Legoas 04] S. Legoas, V. Coluci, S. Braga, P. Coura, S. Dantas, and D. Galvão, "Gigahertz nanomechanical oscillators based on carbon nanotubes,"Nanotechnology 15 (2004) S184-S189.
28. [LACSI 04] "The Path to Extreme Computing," workshop in association with the Los Alamos Computer Science Institute Symposium, October 12, 2004.
29. [Laundauer 61] Landauer, R., "Irreversibility and heat generation in the computing process," IBM J. Res. Dev. 5, 183-191, 1961.
30. [Malone 03] Robert C. Malone, John B. Drake, Philip W. Jones, Douglas A. Rotman, "High-End Computing in Climate Modeling," contribution to SCaLeS report.
31. [Merkle 96] R. Merkel, E. Drexler, "Helical Logic," Nanotechnology (1996) 325-339.
32. [MPI web] See Message Passing Interface (MPI) forum standards documents, http://www.mpi-forum.org/.
33. [NASA 99] R. T. Biedron, P. Mehrotra, M. L. Nelson, F. S. Preston, J. J. Rehder, J. L. Rogers, D. H. Rudy, J. Sobieski, and O. O. Storaasli, "Compute as Fast as the Engineers Can Think!" NASA/TM-1999-209715, available on Internet.
34. [NASA 02] NASA Goddard Space Flight Center, "Advanced Weather Prediction Technologies: NASA's Contribution to the Operational Agencies," available on Internet.
35. [Petrini 03] Fabrizio Petrini, Darren Kerbyson and Scott Pakin, "The Case of the Missing Supercomputer Performance, Achieving Optimal Performance on the 8, 192 processors of ASCI Q," in Proc. of IEEE/ACM SC2003, Phoenix, AZ, November 2003.
36. [Sair 03] Suleyman Sair, Timothy Sherwood, and Brad Calder, "A Decoupled Predictor-Directed Stream Prefetching Architecture," IEEE Transations on Computers, Vol. 52, NO. 3, March 2003.
37. [SCaLeS 03] Workshop on the Science Case for Large-scale Simulation, June 24-25, proceedings on Internet a http://www.pnl.gov/scales/.
38. [Seitz 85] C.L. Seitz, A. Frey, S. Mattisson, S. Rabin, D. Speck, V. van de Snepscheut, "Hot-clock NMOS," in Proc. of the 1985 Chapel Hill Conference on VLSI, 1985.
39. [Sterling 02] Thomas. L. Sterling and H.P. Zima. "Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing." Supercomputing02, Baltimore, Maryland, November 18-22, 2002.
40. [Sunaga 96] Sunaga, T., Peter M. Kogge, et al, "A Processor In Memory Chip for Massively Parallel Embedded Applications," IEEE J. of Solid State Circuits, Oct 1996, pp. 1556-1559.
41. [Timler 03] J. Timler an C.S. Lent, "Maxwell's demon and quantum-dot cellular automata," Journal of Applied Physics 94,1050-1060 (2003).
42. [Tummala 99] Rao R. Tummala and Vijay K. Madisetti, "System on Chip or System on Package?" in IEEE Design and Test of Computers, April 1999, Vol. 16 No. 2, pp. 48-56
43. [Upchurch 03] E. Upchurch, T. Sterling and J. Brockman. "Analysis and Modeling of Advanced PIM Architecture Design Tradeoffs," in Proceedings of the 6th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA03), p66-77, 2003.
44. [Vieri 98] Carlin Vieri, M. Josephine Ammer, Amory Wakefield, Lars 'Johnny' Svensson, William Athas, and Tom Knight, "Designing reversible memory," in C. S. Calude, J. Casti, and M. J. Dinneen, eds., Unconventional Models of Computation, Springer, 1998, pp.386-405.
45. [Vieri 99] Vieri, Carlin, "Reversible Computer Engineering and Architecture," Ph. D. Thesis, Massachusetts Institute of Technology 1999.
46. [Vitanyi 88] Vitanyi, P. M. B., "Locality, communications, and interconnect length in multicomputers," SIAM J. on Computing, 17, 4 (1988), 659-672.
47. [von Neumann 56] von Neumann, J., "Probabilistic Logics and the Synthesis of Reliable Organisms from Unreliable Components," in C. E. Shannon and J. McCarthy, Eds. Automata Studies. Princeton: Princeton University Press, pp. 43-98, 1956.