PCB layout inductance modeling based on a time domain measurement approach

Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC

Volumn 3, Issue , 2004, Pages 1870-1876

  López, Toni ^a   Duerbaum, Thomas ^a   Tolle, Tobias ^a   Elferich, Reinhold ^a  

^a PHILIPS RESEARCH LABORATORIES   (Germany)

Author keywords

High frequency; Lumped element model; Parasitic inductance; PCB layout; SPICE model; Time domain measurement; Transients; Transistor package

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DAMPING; ELECTRIC CURRENTS; ELECTRIC IMPEDANCE; ELECTRIC RESISTANCE; ELECTROMAGNETIC FIELD EFFECTS; FREQUENCIES; OSCILLATIONS; PRINTED CIRCUIT BOARDS; RESISTORS; SWITCHING; TIME DOMAIN ANALYSIS; TRANSIENTS;

HIGH FREQUENCY; LUMPED ELEMENT MODEL; PARASITIC INDUCTANCE; PCB LAYOUT; SPICE MODELS; TIME DOMAIN MEASUREMENTS; TRANSISTOR PACKAGE;

INDUCTANCE;

EID: 2342612875     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APEC.2004.1296122     Document Type: Conference Paper

References (8)

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