On statistical behavior of branch coverage in testing behavioral VHDL models

Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT

Volumn 2000-January, Issue , 2000, Pages 89-94

  Hajjar, A ^a   Chen, T ^a   Von Mayrhauser, A ^b  

^a Department of Mechanical Engineering   (United States)

^b Department of Computer Science   (United States)

Author keywords

Algorithm design and analysis; Computational modeling; Computer science; Computer simulation; Hardware; Software engineering; Software measurement; Software testing; Time to market

Indexed keywords

COMPUTER HARDWARE; COMPUTER SCIENCE; COMPUTER SIMULATION; COMPUTER SOFTWARE; SOFTWARE ENGINEERING; SOFTWARE RELIABILITY; VERIFICATION;

ALGORITHM DESIGN AND ANALYSIS; BEHAVIORAL MODEL; COMPUTATIONAL MODEL; SOFTWARE MEASUREMENT; STATISTICAL BEHAVIOR; STATISTICAL MODELING; TIME TO MARKET; VERIFICATION PROCESS;

SOFTWARE TESTING;

EID: 22944463215     PISSN: 15526674     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HLDVT.2000.889565     Document Type: Conference Paper

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